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Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry / A Hardware-acceleration Protocol Design for Demanding Computations over Multiple CoresBareš, Jan January 2018 (has links)
This work deals with design of communication protocol for data transmission between control computer and computing cores implemented on FPGA chips. The purpose of the communication is speeding the performance demanding software algorithms of non-stream data processing by their hardware computation on accelerating system. The work defines a terminology used for protocol design and analyses current solutions of given issue. After that the work designs structure of the accelerating system and communication protocol. In the main part the work describes the implementation of the protocol in VHDL language and the simulation of implemented modules. At the end of the work the aplication of designed solution is presented along with possible extension of this work.
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Flight Software Development for Demise Observation CapsuleZamouril, Jakub January 2017 (has links)
This work describes the process of the design of a flight software for a space-qualified device, outlines the development and testing of the SW, and provides a description of the final product. The flight software described in this work has been developed for the project Demise Observation Capsule (DOC). DOC is a device planned to be attached to an upper stage of a launch vehicle and observe its demise during atmospheric re-entry at the end of its mission. Due to constraint on communication time during the mission and the need to maximize the amount of transferred data, a custom communication protocol has been developed. / Demise Observation Capsule
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