With the advent of technology in recent years, people depend more on online reviews to purchase a product. It is hard to determine whether the product is good or bad from hundreds of mixed reviews. Also, it is very time-consuming to read many reviews. So, opinion mining of reviews is necessary. The main aim of this project is to convert the reviews of a product into a rating and to evaluate the ratings using machine learning algorithms such as Naïve Bayes and Support Vector Machine. In the process of converting the reviews to a rating, score words are created using SentiWordNet and transformed into seven categories from highly positive to highly negative.

Graphic Processing Units (GPUs) are originally mainly designed to accelerate graphic applications. Now the capability of GPUs to accelerate applications that can be parallelized into a massive number of threads makes GPUs the ideal accelerator for boosting the performance of such kind of general-purpose applications. Meanwhile it is also very promising to apply GPUs to embedded and real-time applications as well, where high throughput and intensive computation are also needed. However, due to the different architecture and programming model of GPUs, how to fully utilize the advanced architectural features of GPUs to boost the performance and how to analyze the worst-case execution time (WCET) of GPU applications are the problems that need to be addressed before exploiting GPUs further in embedded and real-time applications. We propose to apply both architectural modification and static analysis methods to address these problems. First, we propose to study the GPU cache behavior and use bypassing to reduce unnecessary memory traffic and to improve the performance. The results show that the proposed bypassing method can reduce the global memory traffic by about 22% and improve the performance by about 13% on average. Second, we propose a cache access reordering framework based on both architectural extension and static analysis to improve the predictability of GPU L1 data caches. The evaluation results show that the proposed method can provide good predictability in GPU L1 data caches, while allowing the dynamic warp scheduling for good performance. Third, based on the analysis of the architecture and dynamic behavior of GPUs, we propose a WCET timing model based on a predictable warp scheduling policy to enable the WCET estimation on GPUs. The experimental results show that the proposed WCET analyzer can effectively provide WCET estimations for both soft and hard real-time application purposes. Last, we propose to analyze the shared Last Level Cache (LLC) in integrated CPU-GPU architectures and to integrate the analysis of the shared LLC into the WCET analysis of the GPU kernels in such systems. The results show that the proposed shared data LLC analysis method can improve the accuracy of the shared LLC miss rate estimations, which can further improve the WCET estimations of the GPU kernels.

Systems like Google Home, Alexa, and Siri that use voice-based authentication to verify their users’ identities are vulnerable to voice replay attacks. These attacks gain unauthorized access to voice-controlled devices or systems by replaying recordings of passphrases and voice commands. This shows the necessity to develop more resilient voice-based authentication systems that can detect voice replay attacks. This thesis implements a system that detects voice-based replay attacks by using deep learning and image classification of voice spectrograms to differentiate between live and recorded speech. Tests of this system indicate that the approach represents a promising direction for detecting voice-based replay attacks.

Agent-based (AB) and system dynamics (SD) modeling and simulation techniques have been studied and used by various research fields. After the new hybrid modeling field emerged, the combination of these techniques started getting attention in the late 1990's. Applications of using agent-based (AB) and system dynamics (SD) hybrid models for simulating systems have been demonstrated in the literature. However, majority of the work on the domain includes system specific approaches where the models from two techniques are integrated after being independently developed. Existing work on creating an implicit and universal approach is limited to conceptual modeling and structure design. This dissertation proposes an approach for generating AB-SD hybrid models of systems by using Systems Modeling Language (SysML) which can be simulated without exporting to another software platform. Although the approach is demonstrated using IBM's Rational Rhapsody it is applicable to all other SysML platforms. Furthermore, it does not require prior knowledge on agent-based or system dynamics modeling and simulation techniques and limits the use of any programming languages through the use of SysML diagram tools. The iterative modeling approach allows two-step validations, allows establishing a two-way dynamic communication between AB and SD variables and develops independent behavior models that can be reused in representing different systems. The proposed approach is demonstrated using a hypothetical population, movie theater and a real–world training management scenarios. In this setting, the work provides methods for independent behavior and system structure modeling. Finally, provides behavior models for probabilistic behavior modeling and time synchronization.

As part of the approaches used to meet climate goals set by international environmental agreements, policies are being applied worldwide for promoting the uptake of Electric Vehicles (EV)s. The resulting increase in EV sales and the accompanying expansion in the EV charging infrastructure carry along many challenges, mostly infrastructure-related. A pressing need arises to strengthen the power grid to handle and better manage the electricity demand by this mobile and geo-distributed load. Because the levels of penetration of EVs in the power grid have recently started increasing with the increase in EV sales, the real-time management of en-route EVs, before they connect to the grid, is quite recent and not many research works can be found in the literature covering this topic comprehensively. In this dissertation, advances and novel ideas are developed and presented, seizing the opportunities lying in this mobile load and addressing various challenges that arise in the application of public charging for EVs. A Bilateral Decision Support System (BDSS) is developed here for the management of en-route EVs. The BDSS is a middleware-based MAS that achieves a win-win situation for the EVs and the power grid. In this framework, the two are complementary in a way that the desired benefit of one cannot be achieved without attaining that of the other. A Fuzzy Logic based on-board module is developed for supporting the decision of the EV as to which charging station to charge at. GPU computing is used in the higher-end agents to handle the big amount of data resulting in such a large scale system with mobile and geo-distributed nodes. Cyber security risks that threaten the BDSS are assessed and measures are applied to revoke possible attacks. Furthermore, the Collective Distribution of Mobile Loads (CDML), a service with ancillary potential to the power system, is developed. It comprises a system-level optimization. In this service, the EVs requesting a public charging session are collectively redistributed onto charging stations with the objective of achieving the optimal and secure operation of the power system by reducing active power losses in normal conditions and mitigating line congestions in contingency conditions. The CDML uses the BDSS as an industrially viable tool to achieve the outcomes of the optimization in real time. By participating in this service, the EV is considered as an interacting node in the system-wide communication platform, providing both enhanced self-convenience in terms of access to public chargers, and contribution to the collective effort of providing benefit to the power system under the large scale uptake of EVs. On the EV charger level, several advantages have been reported favoring wireless charging of EVs over wired charging. Given that, new techniques are presented that facilitate the optimization of the magnetic link of wireless EV chargers while considering international EMC standards. The original techniques and developments presented in this dissertation were experimentally verified at the Energy Systems Research Laboratory at FIU.

<p>We are given a sequence of jobs on a single machine, and each job has a weight, processing time and a due date. A job is early when it finishes before or on its due date and its earliness is the amount of time between its completion time and its due date. A job is tardy when it finishes after its due date and its tardiness is the amount of time between its due date and its completion time. The TWET problem is to find a schedule which minimizes the total weighted earliness and tardiness. We are focusing on the TWET problem with a constant number of distinct due dates and polynomially related weights. This problem has been proven to be NP-hard. In this thesis, we present a dynamic programming algorithm for our TWET problem first and then convert it into an FPTAS by adopting a rounding scheme.</p> <p>There are several important points in our algorithm: we observe the importance of the straddlers and guess them at the beginning through exhaustive enumeration, and insert them back at the very end by solving a linear problem; we know a series of structural properties of the optimal schedule to shrink the state space of the DP; we increase each due date to get a new problem and adopt a rounding scheme of the DP for the new problem to avoid preemption. Finally we move the due dates back to get the final schedule for the original TWET problem without changing the objective value much.</p> / Master of Science (MSc)

Cloud is becoming the most popular computing infrastructure because it can attract more and more traditional companies due to flexibility and cost-effectiveness. However, privacy concern is the major issue that prevents users from deploying on public clouds. My research focuses on protecting user's privacy in cloud computing. I will present a hardware-based and a migration-based approach to protect user's privacy. The root cause of the privacy problem is current cloud privilege design gives too much power to cloud providers. Once the control virtual machine (installed by cloud providers) is compromised, external adversaries will breach users’ privacy. Malicious cloud administrators are also possible to disclose user’s privacy by abusing the privilege of cloud providers. Thus, I develop two cloud architectures – MyCloud and MyCloud SEP to protect user’s privacy based on hardware virtualization technology. I eliminate the privilege of cloud providers by moving the control virtual machine (control VM) to the processor’s non-root mode and only keep the privacy protection and performance crucial components in the Trust Computing Base (TCB). In addition, the new cloud platform can provide rich functionalities on resource management and allocation without greatly increasing the TCB size. Besides the attacks to control VM, many external adversaries will compromise one guest VM or directly install a malicious guest VM, then target other legitimate guest VMs based on the connections. Thus, collocating with vulnerable virtual machines, or ”bad neighbors” on the same physical server introduces additional security risks. I develop a migration-based scenario that quantifies the security risk of each VM and generates virtual machine placement to minimize the security risks considering the connections among virtual machines. According to the experiment, our approach can improve the survivability of most VMs.

In today's aggressively scaled technology nodes, billions of transistors are packaged into a single integrated circuit. Electronic Design Automation (EDA) tools are needed to automatically assemble the transistors into a functioning system. One of the most important design steps in the physical synthesis is the design of the clock network. The clock network delivers a synchronizing clock signal to each sequential element. The clock signal is required to be delivered meeting timing constraints under variations and in multiple operating modes. Synthesizing such clock networks is becoming increasingly difficult with the complex power management methodologies and severe manufacturing variations. Clock network synthesis is an important problem because it has a direct impact on the functional correctness, the maximum operating frequency, and the overall power consumption of each synchronous integrated circuit. In this dissertation, we proposed synthesis methodologies for robust and reconfigurable clock networks. We have made three contributions to this topic. First, we have proposed a clock network optimization framework that can achieve better timing quality than previous frameworks. Our proposed framework improves timing quality by reducing the propagation delay on critical paths in a clock network using buffer sizing and layer assignment. Second, we have proposed a clock tree synthesis methodology that integrates the clock tree synthesis with the clock tree optimization. The methodology improves timing quality by avoiding to synthesize clock trees with topologies that are sensitive to variations. Third, we have proposed a clock network that can reconfigure the topology based on the active mode of operation. Lastly, we conclude the dissertation with future research directions.

For decades, innovations to surmount the processor versus memory gap and move beyond conventional von Neumann architectures continue to be sought and explored. Recent machine learning models still expend orders of magnitude more time and energy to access data in memory in addition to merely performing the computation itself. This phenomenon referred to as a memory-wall bottleneck, is addressed herein via a completely fresh perspective on logic and memory technology design. The specific solutions developed in this dissertation focus on utilizing intrinsic switching behaviors of embedded MRAM devices to design cross-layer and energy-efficient Compute-in-Memory (CiM) architectures, accelerate the computationally-intensive operations in various Artificial Neural Networks (ANNs), achieve higher density and reduce the power consumption as crucial requirements in future Internet of Things (IoT) devices. The first cross-layer platform developed herein is an Approximate Generative Adversarial Network (ApGAN) designed to accelerate the Generative Adversarial Networks from both algorithm and hardware implementation perspectives. In addition to binarizing the weights, further reduction in storage and computation resources is achieved by leveraging an in-memory addition scheme. Moreover, a memristor-based CiM accelerator for ApGAN is developed. The second design is a biologically-inspired memory architecture. The Short-Term Memory and Long-Term Memory features in biology are realized in hardware via a beyond-CMOS-based learning approach derived from the repeated input information and retrieval of the encoded data. The third cross-layer architecture is a programmable energy-efficient hardware implementation for Recurrent Neural Network with ultra-low power, area-efficient spin-based activation functions. A novel CiM architecture is proposed to leverage data-level parallelism during the evaluation phase. Specifically, we employ an MRAM-based Adjustable Probabilistic Activation Function (APAF) via a low-power tunable activation mechanism, providing adjustable accuracy levels to mimic ideal sigmoid and tanh thresholding along with a matching algorithm to regulate neuronal properties. Finally, the APAF design is utilized in the Long Short-Term Memory (LSTM) network to evaluate the network performance using binary and non-binary activation functions. The simulation results indicate up to 74.5 x 215; energy-efficiency, 35-fold speedup and ~11x area reduction compared with the similar baseline designs. These can form basis for future post-CMOS based non-Von Neumann architectures suitable for intermittently powered energy harvesting devices capable of pushing intelligence towards the edge of computing network.

REpresentational State Transfer or REST is the software architecture style most commonly used for Web Application Programming Interfaces (APIs) and was first defined in 2000 by Roy Thomas Fielding in his PhD dissertation Styles and the Design of Network-based Software Architectures and became a standard for the design of the early World Wide Web and Web-based software. The REST standard continues to be influential in the design of Web systems today, however, it was defined over 15 years ago when the Web was still in its infancy. This paper analyzes REST as it was originally defined by Fielding in 2000 and investigates the validity of its original principles in the modern Internet and Web APIs by sampling a number of prominent APIs and their use of REST. REST definitely has drawbacks for certain types of APIs as evidenced by deviations in the majority of sampled APIs. It is not popular with services that are difficult to represent in REST's resource model. However, REST’s popularity has not noticeably decreased since it was defined rather it has most likely increased. Additionally, each use case that is unsupported by REST goes against some REST constraints that crucial in other areas of it implementation. In conclusion, RESTful properties were not only relevant in the late 1990s and early 2000s but continue to be relevant today as evidenced by its continued widespread use by reputable Web APIs.