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1	SIMULATION OF A MODULAR HIERARCHICAL ADAPTIVE COMPUTER ARCHITECTURE WITH COMMUNICATION DELAY Wang, I-Yang, 1958- January 1986 (has links) No description available. Computer architecture.
2	Assigning cost to branches for speculation control in superscalar processors Khosrow-Khavar, Farzad 10 April 2008 (has links) No description available. Computer architecture
3	Using lazy instruction prediction to reduce processor wakeup power dissipation Homayoun, Houman 10 April 2008 (has links) No description available. Computer architecture
4	Performance and energy efficiency of clustered processors Zarrabi, Sepehr 10 April 2008 (has links) Modern processors aim to achieve ILP by utilizing numerous functional units, large onchip structures and wider issue windows. This leads to extremely complex designs, which in turn adversely affect clock rate and energy efficiency. Hence, clustered processors have been introduced as an alternative, which allow high levels of ILP while maintaining a desirable clock rate and manageable power consumption. Nonetheless, clustering has its drawbacks. In this work we discuss the two types of clustering-induced delays caused by limited intra-cluster issue bandwidth and inter-cluster communication latencies. We use simulation results to show that the stalls caused by inter-cluster communication delays are the dominant factor impeding the performance of clustered processors. We also illustrate that microarchitectures become more energy efficient as the number of clusters grows. We study branch misprediction as a source of energy loss and examine how pipeline gating can alleviate this problem in centralized and distributed processors. Computer architecture
5	A dual-ported real memory architecture for the g-machine Rankin, Linda J. 08 1900 (has links) (PDF) M.S. / Computer Science & Engineering / A dual-ported real memory architecture is described which supports the requirements of a list-processing evaluator, the G-machine. The architecture provides support for allocating available nodes and a concurrent garbage collection scheme. This scheme uses reference counts and requires traversal of sub-graphs to collect cyclic structures. The architecture requires only one customized hardware component that provides support for maintaining reference counts. Simulation of the architecture shows that it is efficient and meets the requirements of the G-machine given certain assumptions about the number and size of sub-graphs that are traversed. Cyclic structure information provided by the compiler would reduce the number of sub-graphs requiring traversal. Simulation shows that this optimization improves performance of the design, particularly for allocation rates greater than 100K nodes per second. Computer architecture
6	Viable software : the intelligent control paradigm for adaptable and adaptive architecture / Herring, Charles Edward. January 2002 (has links) Thesis (Ph. D.)--University of Queensland, 2002. / Includes bibliographical references. Computer architecture.
7	The design and programming of a powerful short-wordlength processor using context-dependent machine instructions / Hor, Tze-man. January 1985 (has links) Thesis--M. Phil., University of Hong Kong, 1985. Computer architecture.
8	Floating-point fused multiply-add architectures Quinnell, Eric Charles 28 August 2008 (has links) Not available / text Computer architecture
9	Floating-point fused multiply-add architectures Quinnell, Eric Charles, 1982- 22 August 2011 (has links) Not available / text Computer architecture
10	The design and programming of a powerful short-wordlength processor using context-dependent machine instructions Hor, Tze-man, 賀子文 January 1985 (has links) published_or_final_version / Computer Science / Master / Master of Philosophy Computer architecture.

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