The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made packet-switched networks-on-chip (NoCs) a more compelling choice for the communication backbone in next-generation systems. NoC designs are sensitive to many design parameters—hence the study of new NoCs can be time-intensive. We propose DART, a fast and flexible FPGA-based NoC simulation architecture. Rather than laying the NoC out directly on the FPGA like previous approaches, DART virtualizes the NoC by mapping its components to a generic NoC simulation engine. This approach has two main advantages: (i) since it is virtualized it can simulate any NoC; and (ii) any NoC can be mapped to the engine without the time-consuming process of rebuilding the FPGA design. We demonstrate that an implementation of DART on a Virtex-II Pro FPGA achieves over 100x speedup over the cycle-based software simulator Booksim, while maintaining the same level of simulation accuracy.

The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made packet-switched networks-on-chip (NoCs) a more compelling choice for the communication backbone in next-generation systems. NoC designs are sensitive to many design parameters—hence the study of new NoCs can be time-intensive. We propose DART, a fast and flexible FPGA-based NoC simulation architecture. Rather than laying the NoC out directly on the FPGA like previous approaches, DART virtualizes the NoC by mapping its components to a generic NoC simulation engine. This approach has two main advantages: (i) since it is virtualized it can simulate any NoC; and (ii) any NoC can be mapped to the engine without the time-consuming process of rebuilding the FPGA design. We demonstrate that an implementation of DART on a Virtex-II Pro FPGA achieves over 100x speedup over the cycle-based software simulator Booksim, while maintaining the same level of simulation accuracy.