Session Initiation Protocol (SIP) is fast emerging as the next generation signaling protocol. It operates independently of the underlying network transport protocol, establishing sessions between multiple users irrespective if the media is voice, data or video. It is projected to eventually replace the existing multiple voice and video signaling protocols as a single protocol which achieves all. SIP implements a non-trivial grammar. Parsing this grammar to extract the protocol fields proves to be a high overhead for the CPU. This paper presents hardware offload architecture; the SIP Offload Engine (SOE) which essentially extracts the SIP fields and stores them is a proprietary data structure, for easy access by the CPU. An analysis has been done which shows a reduction in the CPU overhead by as much as 90%.

This dissertation implements a Network Based Intrusion Detection System on a Dynamically Reconfigurable Architecture. The design is captured using synthesizable Verilog HDL. The Dynamically Reconfigurable Intrusion Detection System (DRIDS) addresses the challenges faced by typical applications that use Reconfigurable devices that do not exploit their full computational density because of the limited FPGA memory, inefficient FPGA utilization, processor to FPGA communication bottlenecks and high reconfiguration latencies. The implementation of Intrusion Detection on the DRIDS boasts of high computational density and better performance through the exploitation of parallelism inherent in this application.

The advent of multi-processor systems has motivated programmers to develop multi-threaded and multi-process applications on shared memory data structures. In these applications, multiple processes read and update shared data structure concurrently, which may lead to race conditions resulting in incoherent memory. To ensure exclusivity of access to this shared memory, programmers have been using locks. Lock-based concurrency is a pessimistic approach that assumes conflicts among concurrent processes to occur frequently.However, if few conflicts occur, lock-based concurrency unnecessarily reduce concurrency. One solution to improve concurrency, is to allow non-conflicting processes to execute in parallel. This can be gained by using fine locks, but programming with them is complex and error-prone. Consequently, researchers have devised an optimistic concurrency mechanism known as lock-free algorithms. Various lock-free libraries have been developed that are either data structure specific or universal constructs. However, these lock-free libraries have been restricted to simple data structures that do not meet the requirements of a real-world application. This work focuses on implementing a lock-free data structure suitable for a real-world application. The suitability of various implementations is analyzed. Design choices are made based upon the requirements and the suitability of lock-free implementations to the specific application considered. Finally, the performance of the lock-free implementation versus lock-based implementation are compared. Along with it, certain insights related to reduced complexity of the implementation and atomicity of lock-free implementation that make it robust are discussed.

Mobility computing is the network-access paradigm of the future. Future network protocols will be 4G defined over an entirely packet-switched network with digital network elements, high bandwidth and built-in network security. The bandwidth provided will be 100Mbps for stationary objects and 20 Mbps while in motion. 4G wireless networks will support global roaming and service portability across multiple wireless and mobile networks, for example from a cellular network to a satellite-based network to a high-bandwidth wireless LAN. TCP Performance degrades severely on a wireless link due to higher Bit Error Rate, Mobility, Limited Capacity, Non Uniform Error Profile and frequent Disconnections. We propose a new transport layer protocol for 4G Wireless Systems, compatible with the existing TCP/ IP implementations that combines the best of the currently proposed algorithms and our own new congestion control algorithm. We designed an optimized congestion control algorithm for the wireless link that provides connection oriented, reliable data service with graceful handovers and ability to recover from frequent disconnections. The protocol deals with high bit error rate by implementing split connections with local fast retransmissions. It uses Zero Window Advertisement to accomplish smooth handover under inter-wireless cell mobility. Several other methods have been proposed to overcome TCP-over-wireless faults including split-TCP connection, triple-acknowledgements and acknowledgment caching. Each of these methods improves the efficiency of TCP by improving a single fault aspect, while our proposal combines compatible improvements into an efficient and reliable protocol.

Many contemporary servers, personal and laptop computers, and even cell phones are powered by high-performance superscalar processors. In the past, conventional microarchitecture and technology scaling has afforded leaps in their performance and functionality. Today, conventional microarchitecture and technology scaling are both yielding lower returns with increasing costs. Therefore, any microarchitecture level decision to increase performance needs to be critically analyzed from a technology standpoint. To address this critical need, we have developed a register transfer level (RTL) model of a superscalar microarchitecture with similar complexity of a current generation processor. The RTL model is written in Verilog and is fully synthesizable. The model can be implemented in different technology nodes using a well established ASIC design flow to provide high fidelity estimation of propagation delay, power consumption, area, and other technology related costs. The RTL model is supplemented with a register file compiler to estimate the costs of multi-ported memory structures which are extensively used in a superscalar microarchitecture. The RTL model is also tightly integrated with a C++ functional simulator to assist and accelerate verification.

For many applications a common source of performance degradation is excessive processor stalling from high memory latencies or poor data placement. Performance degradations from program and memory hierarchy interactions are often difficult for programmers and compilers to correct due to a lack of run-time information or limited knowledge about the underlying problem. By leveraging the Pentium 4 processor's performance monitoring hardware, specific run-time information can be provided, allowing code modifications to reduce or even eliminate problematic code, resulting in reduced execution times. <br>Furthermore, many tools currently available to aid programmers are program counter centric. These tools point out which area of the code produce slowdowns, but they do not directly show where the problem data structures are. This is a common problem in programs that dynamically allocate memory. By creating a ?malloc-centric? tool, we can develop an interesting perspective of the memory behavior of the system, providing better insight into the sources of performance problems.

Using a communication network, such as an IP network, in the control loop is increasingly becoming the norm. This process of network-based control (NBC) has potential profound impact in areas such as: teleoperation, healthcare, military applications, and manufacturing. However, limitations arise as the communication network introduces delay that often degrades or destabilizes the control system. Four methods have been investigated that alleviate the IP network delays to provide stable real-time control. A performance measure is defined for a case study on a DC motor with a networked proportional-integral (PI) speed controller with various network delays and noise levels. Matlab simulation results show that NBC combined with these techniques can successfully maintain system stability, allowing control of real-time applications.

In modern communication systems, wireless ad hoc networking has become an irreplaceable technology where communication infrastructure is insufficient or unavailable. An ad hoc network is a collection of self-organizing nodes that are rapidly deployable and adaptable to frequent topology changes. In this dissertation, the key problems related to the network layer (i.e., forwarding, routing, and network-layer topology control) are addressed. The problem of unfair forwarding in ad hoc nodes is identified and cross-layer solutions are proposed. Because a typical ad hoc node functions both as a router and a host, severe unfairness occurs between originated and forwarded packets which eventually leads to a serious starvation problem. The results show that, to restore the fairness and enhance the capacity efficiency, non-traditional queueing schemes are required where both the network and the MAC layers should be considered together. Routing is a critical protocol, which directly affects the scalability and reliability of wireless ad hoc networks. A good routing protocol for wireless ad hoc networks should overcome the dynamic nature of the topology arising from unreliable wireless links and node mobility. In ad hoc networks, it is very important to balance the route accuracy and overhead efficiency. A number of routing protocols have been proposed for wireless ad hoc networks, but it is well known that current routing protocols scale poorly with the number of nodes, the number of traffic flows, the intensity of mobility. The main objective of this dissertation is to provide efficient routing protocols for different types of wireless ad hoc networks including wireless mesh networks (WMNs), mobile ad hoc networks (MANETs), and wireless sensor networks (WSNs). Since each category has different assumptions and constraints, different solutions should be considered. WMNs and WSNs have low mobility and centralized (one-to-any) traffic patterns while MANETs have relatively high mobility and uniform (any-to-any) traffic patterns. WSNs are highly resource-constrained while WMNs are not. A new routing protocol specially designed for WMNs is proposed. Simulation experiments show that the protocol outperforms existing generic ad hoc routing protocols. This improvement is enabled by the essential characteristics of WMNs, and as a result, the protocol does not rely on bandwidth-greedy flooding mechanism. For MANET routing, an existing de facto the standard Internet intra-AS (autonomous system) routing protocol is extended to enhance the scalability in ad hoc environments. When extended for MANETs, Open Shortest Path First (OSPF) is expected to provide the benefits of maturity, interoperability, and scalability. The scalability extension is two-fold: the notions of distance effect and multiple areas are explored as extensions. Both approaches provide significant gain in scalability by efficiently reducing flooding overhead without compromising routing or forwarding performance. Finally, a new scalable and reliable sensor network routing is proposed. Since WSNs are the most resource-constrained type of ad hoc networks, the protocol should be very simple yet reliable. The proposed WSN routing protocol is designed to provide reliability (via multi-path redundancy), scalability (with efficiently contained flooding), and flexibility (source-tunable per-packet priority), which are achieved without adding protocol complexity or resource consumption. The protocol is implemented on real sensor motes and its performance is tested through outdoor sensor field deployments. The results show that the protocol outperforms even sophisticated link estimation based sensor network routing protocols.

The use of three dimensional chip fabrication technologies has emerged as a solution to the difficulties involved with the continued scaling of bulk silicon devices. While the technology exists, it is undervalued and underutilized largely due to the design and verification challenges a complex 3D design presents. This work presents a clock tree insertion and timing verification methodology for three dimensional integrated circuits (3DIC). It has been designed in the context of and incorporated into the 3DIC design methodology also developed within our research group. The 3DIC verification methodology serves as an efficient means to perform all setup and hold timing checks harnessing the power of existing commercial chip design and verification tools. A novel approach is presented in which the multi-die design is temporarily transformed to appear as a traditional 2D design to the commercial tools for verification purposes. Various parasitic extraction algorithms are examined, and we present a method for performing accurate 3D parasitic extraction for timing purposes. We offer theoretical insight into the optimization of a 3D clock tree for power savings and coupling-induced delay minimization. A practical example of the 3DIC design and verification flow is detailed through the explanation of our research group?s test chip, a nearly 140,000 cell 3D fast Fourier transform chip currently awaiting fabrication at MIT?s Lincoln Labs.

We consider the problem of using the real-time measurements of the network elements for connection admission control on QoS aware networks. Our objective is to study the measurement process and determine the real-time utilization of a link, and use these measurements to determine the admission of new flows into the network, while providing statistical guarantees on the QoS ensured for the existing admitted flows. First we survey the vast amount of existing literature in the field and identify the components of a measurement-based admission control system, and the various factors which affects the performance of an algorithm. We use the ns-2 simulator to simulate some of the proposed (though not all) algorithms and test the performance of these algorithms for various arrival processes at the connection level. We use the results from these simulations to verify the performance claims of the various algorithms, and use the performance tuning parameters to find optimal performance regions. We study the buffer dynamics at the burst level and analyze the loss caused by admitting excessive flows. Our work extends from the existing literature in studying the effect of different arrival processes on the blocking probabilities of new flows and surveying an ad-hoc mix-and-match approach of the estimation technique and decision process to explore a higher performance benchmark.