The study investigates various load balancing strategies to improve the performance of distributed computer systems. A static task allocation and a number of dynamic load balancing algorithms are proposed, and their performances evaluated through simulations. First, in the case of static load balancing, the precedence constrained scheduling heuristic is defined to effectively allocate the task systems with high communication to computation ratios onto a given set of processors. Second, the dynamic load balancing algorithms are studied using a queueing theoretic model. For each algorithm, a different load index has been used to estimate the host loads. These estimates are utilized in simple task placement heuristics to determine the probabilities for transferring tasks between every two hosts in the system. The probabilities determined in this way are used to perform dynamic load balancing in a distributed computer system. Later, these probabilities are adjusted to include the effects of inter-host communication costs. Finally, network partitioning strategies are proposed to reduce the communication overhead of load balancing algorithms in a large distributed system environment. Several host-grouping strategies are suggested to improve the performance of load balancing algorithms. This is achieved by limiting the exchange of load information messages within smaller groups of hosts while restricting the transfer of tasks to long distance remote hosts which involve high communication costs. Effectiveness of the above-mentioned algorithms is evaluated by simulations. The model developed in this study for such simulations can be used in both static and dynamic load balancing environments.

The 2D and 3D graphics support for PC's and workstations is becoming a very challenging field. The need to continuously support real time image generation at higher frame rates and resolutions implies that all levels of the graphics generation process must continuously improve. New hardware algorithms need to be devised and the existing ones must be optimised for better performance. These algorithms must exploit parallelism in every possible way and new hardware architectures and memory configurations must accompany them to support this kind ofparallelism. This thesis focuses on new hardware techniques, of both architectural and algorithmic nature, to accelerate the 2D and 3D graphics performance of computer systems. Some of these new techniques are in the frame buffer access level, where the images are stored in the video memory and then displayed on the screen. Some are in the rasterisation level where the drawing of basic primitives such as lines, triangle and polygons takes place. Novel rasterisation algorithms are invented and compared with traditional ones in terms of hardware complexity and performance and their basic models have been implemented in VHDL and in other software languages. New frame buffer architectures are introduced and analysed that can improve the overall performance of a graphics system significantly and are compatible with a number of graphics systems in terms of their requirements. During the development of this thesis special consideration was given to the hardware (e. g. VHDL register-transfer level) implementation of the described architectures and algorithms. Both software, hardware models and their test environments were implemented in a way to maximise the accuracy of the results. The reason for that was to make sure that actual hardware implementation would be possible and it would produce the same results without any surprises

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Technological advances in both local area networks and computer processor design have led to multiple computer installations being composed of a much wider range of network devices than previously possible. High bandwidth computer networks may now interconnect large numbers of devices that have different processor architectures and instruction sets, as well as various levels of performance. This thesis is concerned with the merits of such networks and addresses the problem of how the many different types of computers may be integrated to form a unified system. A review of a number of approaches towards the formation of multiple computer .systems includes campus computer networks, configurations of mainframes and examples of distributed computer systems. This study provides an insight into the fundamental principles of this field. The key features of the systems considered in the study are grouped together in a description of a general network structure. Subsequently, the network devices in this structure are classified into three groups, according to their roles and communication requirements. The three-way classification of devices leads to the development of a Triadic Network Model to describe the interactions within and between the three groups. The model's specification of network communication provides the basis for protocols that are well suited to the needs of this computing environment. The thesis covers the principles of the protocols and the details of their implementation in an experimental system. The software tools developed to support the implementation are also described.

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This thesis presents the design of an Ethernet local-area network interface for embedded transputer systems. It is based upon parallel software which manages the TCP/IP family of protocols, passing packets between a single transputer, which connects to the network, and application processes which run on an arbitrary number of other transputers. The different layers of the protocol processing - Ethernet control, IP and TCP are all performed in separate parallel processes. Extra routing processors, arranged in a tree configuration, provide access to the lower IP and Ethernet layers from as many TCP and application processes as desired. Investigation of the processor utilisation and channel throughput of each of the parallel processes has led to the rejection of hardware-assistance in the form of a complex shared-memory, multi-processor architecture. Instead, a double pipeline of processes, running on a small pipeline of transputers, communicate exclusively using the transputers' serial links. This scheme is shown to provide good load balancing and to be a cost-effective way of exchanging traffic between a transputer application and a user process running on a high-performance workstation at data rates of over 950 kbytes/second - almost the entire available bandwidth of a 10 Mbit/sec Ethernet. All software is written in the occam programming language. As well as presenting the design of the protocol software, the thesis includes performance measurements and reports on two applications which were built upon the initial work. These are a networked implementation of the INMOS Iserver, which allows access to transputers from anywhere on the network, and an embedded instrumentation system which pre-processes data from an ion microbeam and passes part-analysed results to a conventional workstation for display, archiving and user control of the experiment.

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