Global ETD Search

1	Tolerating processor-memory performance gap Lai, Shih-Chang 31 October 2002 (has links) While the performance gap between microprocessors and main memory is ever increasing each year, cache memory has been a bridge to alleviate this discrepancy. In this thesis proposal, we introduce three techniques to tolerate this processor and memory speed imbalance. First, we propose the bloom filter scheme to identify which load operant could cause cache miss. Second, we explore a new fault-tolerant microarchitecture to detect transient error occurs. Third, we proposed a novel hardware-only mechanism to solve pointer-chasing problem in Link-list Data Structure application. The simulation shows that the bloom filter may filter out 99% of cache miss. The new fault-tolerant microarchitecture reduce the penalty caused by detecting instruction error about 1.8-13%. The hardware-only data prefetch mechanism accurate predict over 80% of irregular address pattern and improve the performance by 7%. / Graduation date: 2003 Computer storage devices
2	Optimum load factors for files Pool, Jan Albertus van der, January 1973 (has links) Thesis--Universiteit te Leyden. / "Stellingen" ([3] p.) inserted. Summary in Dutch. Includes bibliographical references (p. 107-109). Computer storage devices.
3	Availability and performance analysis of data hot-spots in distributed storage systems a thesis presented to the faculty of the Graduate School, Tennessee Technological University / Langston, Jeremy W., January 2009 (has links) Thesis (M.S.)--Tennessee Technological University, 2009. / Title from title page screen (viewed on Mar. 12, 2010). Bibliography: leaves 70-77. Computer storage devices
4	A fast access electronic memory system Featherston, John Richard, 1928- January 1957 (has links) No description available. Computer storage devices.
5	A first-in-first-out memory Varga, John Cleo, 1945- January 1976 (has links) No description available. Computer storage devices.
6	A tree coding content addressable memory Vilmansen, Toomas Rein January 1970 (has links) This thesis describes the properties of a memory in which locations are software addressed using a tree. The properties investigated were chiefly concerned with the practical issues of memory usage and access time. Investigations of these properties were made by using statistically different inputs to a computer model of the memory. The most probable tree structure for one type of input was calculated. It is concluded that the software tree, with uniform distribution input requires more memory capacity than a normal storage scheme. On the other hand, the access time can be much reduced. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate Computer storage devices.
7	IPU/LTB:a method for reducing effective memory latency Harmon, C. Reid, Jr. 01 December 2003 (has links) No description available. Computer storage devices Cache memory
8	IPU/LTB a method for reducing effective memory latency / Harmon, C. Reid, January 2003 (has links) (PDF) Thesis (Ph. D.)--College of Computing, Georgia Institute of Technology, 2004. Directed by Ken MacKenzie. / Vita. Includes bibliographical references (leaves 135-146). Computer storage devices. Cache memory.
9	Improving magneto-optic data storage densities using nonlinear equalization Gupta, Sunil 28 August 2008 (has links) Not available / text Computer storage devices Magnetooptical devices
10	Design of a floating point processor for the PDP-9 computer Huey, Ben Milton, 1945- January 1969 (has links) No description available. Computer storage devices. Hybrid computers.

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