A software component model is the cornerstone of any Component-based Software Development (CBSD) methodology. Such a model defines the modelling elements for constructing software systems. In software system modelling, it is necessary to capture the three elements of a system's behaviour: (i) control (ii) computation and (iii) data. Within a system, computations are performed according to the flow of control or the flow of data, depending on whether computations are control-driven or data-driven. Computations are function evaluations, assignments, etc., which transform data when invoked by control or data flow. Therefore a component model should be able to model control flow, data flow as well as computations. Current component models all model computations, but beside computations tend to model either control flow only or data flow only, but not both. In this thesis, we present a new component model which can model both control flow and data flow. It contains modelling elements that capture control flow and data flow explicitly. Furthermore, the modelling of control flow is separate from that of data flow; this enables the modelling of both control-driven and data-driven computations. The feasibility of the model is shown by means of an implementation of the model, in the form of a prototype tool. The usefulness of the model is then demonstrated for a specific domain, the embedded systems domain, as well as a generic domain. For the embedded systems domain, unlike current models, our model can be used to construct systems that are both control-driven and data-driven. In a generic domain, our model can be used to construct domain models, by constructing control flows and data flows which together define a domain model.

Asynchronous design is a possible alternative design methodology that has the ability to alleviate issues associated with clock skew, power dissipation, and process and environmental variability among transistors, issues encountered in typical synchronous design methodologies. This investigation studies the implementation of two asynchronous models of the Texas Instruments MSP430 processor family using a logic system known as Null Convention Logic (NCL). The study also investigates two design styles of NCL: the data-driven and control-driven design styles. This example and others show that although there are tradeoffs in chip area and performance, the control-driven design style is a viable methodology that can lead to designs that are low in energy usage. The openMSP430 processor project is the baseline for the investigation as it is a mature open-source project. Silicon-proven multiple times and fully synthesizable, it parallels the original Texas Instruments family nearly cycle for cycle. UNCLE (Unified NCL Environment) is a toolset used to create comparable implementations of the openMSP430 architecture that are data-driven and control-driven in nature. This investigation shows that the control-driven implementation has a slightly larger chip area due to the complexity of the control path and its effects on the data path. While the control path has a lower area than the data-driven model due to area optimization, the data path of the control-driven version is larger than that of the data-driven model. Because of these issues of complexity in both the control and data paths, the performance of the model suffers as well, degrading from the already poor performance of the traditional data-driven NCL model. Along with the increase in chip area and the decrease in performance, the control-driven model sees a 50.2% average decrease in energy usage as compared to the data-driven model. As with most design choices in engineering, there are tradeoffs when using either design style of NCL. This investigation serves to allow designers to make a well-informed decision when deciding between the two.