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Five new single-stage power factor correction (PFC) techniques are developed for single-phase applications. These converters are: Integrated single-stage PFC converters, voltage source charge pump power factor correction (VS-CPPFC) converters, current source CPPFC converters, combined voltage source current source (VSCS) CPPFC converters, and continuous input current (CIC) CPPFC converters. Integrated single-stage PFC converters are first developed, which combine the PFC converter with a DC/DC converter into a single-stage converter. DC bus voltage stress at light load for the single-stage PFC converters are analyzed. DC bus voltage feedback concept is proposed to reduce the DC bus voltage stress at light load. The principle of operations of proposed converters are presented, implemented and evaluated. The experimental results verify the theoretical analysis. VS-CPPFC technique use a capacitor in series with a high frequency voltage source to achieve the PFC function. In this way, the input inductor is eliminated. VS-CPPFC AC/DC converters are developed, and their performance is evaluated. VS-CPPFC electronic ballasts with and without dimming function are also presented. The average lamp current control with duty ratio modulation is developed so that the lamp operates in constant power with a low crest factor over the line variation. The experimental results verify the CPPFC concept. CS-CPPFC technique employs a capacitor in parallel with a high frequency current source to obtain the PFC function. The unity power factor condition and principle of operation are analyzed. By doing so, the switch has less switching current stress, and deals only with the resonant inductor current. Design considerations and experimental results of the CS-CPPFC electronic ballast are presented. VSCS-CPPFC technique integrates the VS-CPPFC with the CS-CPPFC converters. The circuit derivation, unity power factor condition and design considerations are presented. The developed VSCS-CPPFC converters has constant lamp operation, low crest factor with a high power factor even without any feedback control. CIC-CPPFC technique is developed by inserting a small inductor in series with the line rectifier for the conceptual VS-CPPFC, CS-CPPFC and VSCS-CPPFC circuits. The circuit derivation and its unity power factor condition are discussed. The input current can be designed to be continuous, and a small line input filter can be used. The circulating current in the resonant tank and the switching current stress are minimized. The average lamp current control with switching frequency modulation is developed, so the developed electronic ballast operates in constant power, low crest factor. The developed CIC-CPPFC electronic ballast has features of low line input current harmonics, constant lamp power, low crest factor, continuous input current, low DC bus voltage stress, small circulating current and switching current stress over a wide range of line input voltage. / Ph. D.

The conventional power factor correction circuit has a fixed output voltage. However, in some applications, a PFC circuit with a wide output voltage range is needed. A single phase power factor correction circuit with wide output voltage range is developed in this work. After a comparison of two main power stage candidates (Buck+Boost and Sepic) in terms of efficiency, complexity, cost and device rating, the buck+boost converter is employed as the variable output PFC power stage. From the loss analysis, this topology has a high efficiency from light load to heavy load. The control system of the variable output PFC circuit is analyzed and designed. Charge average current sensing scheme has been adopted to sense the input current. The problem of high input harmonic currents at low output voltage is discussed. It is found that the current loop gain and cross over frequency will change greatly when the output voltage changes. To solve this problem, an automatic gain control scheme is proposed and a detailed circuit is designed and added to the current loop. A modified input current sensing scheme is presented to overcome the problem of an insufficient phase margin of the PFC circuit near the maximum output voltage. The charge average current sensing circuit will be bypassed automatically by a logical circuit when the output voltage is higher than the peak line voltage. Instead, a resistor is used to sense the input current at that condition. Therefore, the phase delay caused by the charge average current sensing circuit is avoided. The design and analysis are based on a novel air conditioner motor system application. Some detailed design issues are discussed. The experimental results show that the variable output PFC circuit has good performance in the wide output voltage range, under both the Boost mode when the output voltage is high and the Buck+Boost mode when the output voltage is low. / Master of Science

A constant switching frequency with the sixth-order harmonic injection PWM concept is established, and a sixth-order harmonic injection technique is developed for the harmonic reduction of a single-switch three-phase boost rectifier. The approach employs a constant duty cycle with sixth-order harmonic injection to suppress the dominant (fifth-order) harmonic in the input currents. Hence, to meet the THD<10% requirement, the rectifier voltage gain can be designed down to 1.45; to meet the IEC 1000-3-2 (A) standard, the output power can be pushed up to 10 kW for the application with a 3X220 V input and a 800 V output. The results are verified on a 6-kW prototype. The injection principle is graphically explained in current waveforms and mathematically proved. Two injection methods are proposed to meet either the THD requirement or the IEC standard. The injection implementation and design guidelines are provided. The boost inductor design and EMI filter design are discussed. An average small- signal model based on the equivalent multi-module model is developed and experimentally verified. The variations of the small-signal model against load are demonstrated, and the compensator design is discussed. The results show that at no load, the dominant pole of the control-to-output transfer function approaches the origin and causes more phase delay, making the control design difficult. To avoid the no load case and to simplify the control design, a 50-W dummy load (1% of the full load) is added. Finally, a simple nonlinear gain control circuit is presented to mitigate the load effect and reduce the dummy load to 10 W. / Master of Science

In the legal domain, depositions help lawyers and paralegals to record details and recall relevant information relating to a case. Depositions are conversations between a lawyer and a deponent and are generally in Question-Answer (QA) format. These documents can be lengthy, which raises the need for applying summarization methods to the documents. Though many automatic summarization methods are available, not all of them give good results, especially in the legal domain. This creates a need to process the QA pairs and develop methods to help summarize the deposition. For further downstream tasks like summarization and insight generation, converting QA pairs to canonical or declarative form can be helpful. Since the transformed canonical sentences are not perfectly readable, we explore methods based on heuristics, language modeling, and deep learning, to improve the quality of sentences in terms of grammaticality, sentence correctness, and relevance. Further, extracting important entities and keywords from a deposition will help rank the candidate summary sentences and assist with extractive summarization. This work investigates techniques for enhanced generation of canonical sentences and extracting relevant entities and keywords to improve deposition summarization. / Master of Science / In the legal domain, depositions help lawyers and paralegals to record details and recall relevant information relating to a case. Depositions are conversations between a lawyer and a deponent and are generally in Question-Answer format. These documents can be lengthy, which raises the need for applying summarization methods to the documents. Typical automatic summarization techniques perform poorly on depositions since the data format is very different from standard text documents such as news articles, blogs. To standardize the process of summary generation, we convert the Question-Answer pairs from the deposition document to their canonical or declarative form. We apply techniques to improve the readability of these transformed sentences. Further, we extract entities such as person names, locations, organization and keywords from the deposition to retrieve important sentences and help in summarization. This work describes the techniques used to correct transformed sentences and extract important entities and keywords to improve the summarization of depositions.

ITC/USA 2007 Conference Proceedings / The Forty-Third Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2007 / Riviera Hotel & Convention Center, Las Vegas, Nevada / Next generation satellite communication systems require efficient coding schemes that enable high data rates, require low overhead, and have excellent bit error rate performance. A newly rediscovered class of block codes called Low Density Parity Check (LDPC) codes has the potential to revolutionize forward error correction (FEC) because of the very high coding rates. This paper presents a brief overview of LDPC coding and decoding. An LDPC algorithm developed by Goddard Space Flight Center is discussed, and an overview of an accompanying VHDL development by L-3 Communications Cincinnati Electronics is presented.

Recent large-scale document digitization initiatives have created new modes of access to modern library collections with the development of new hardware and software technologies. Most commonly, these digitization projects focus on accurately scanning bound texts, some reaching an efficiency of more than one million volumes per year. While vast digital collections are changing the way users access texts, current scanning paradigms can not handle many non-standard materials. Documentation forms such as manuscripts, scrolls, codices, deteriorated film, epigraphy, and rock art all hold a wealth of human knowledge in physical forms not accessible by standard book scanning technologies. This great omission motivates the development of new technology, presented by this thesis, that is not-only effective with deteriorated bound works, damaged manuscripts, and disintegrating photonegatives but also easily utilized by non-technical staff. First, a novel point light source calibration technique is presented that can be performed by library staff. Then, a photometric correction technique which uses known illumination and surface properties to remove shading distortions in deteriorated document images can be automatically applied. To complete the restoration process, a geometric correction is applied. Also unique to this work is the development of an image-based uncalibrated document scanner that utilizes the transmissivity of document substrates. This scanner extracts intrinsic document color information from one or both sides of a document. Simultaneously, the document shape is estimated to obtain distortion information. Lastly, this thesis provides a restoration framework for damaged photographic negatives that corrects photometric and geometric distortions. Current restoration techniques for the discussed form of negatives require physical manipulation to the photograph. The novel acquisition and restoration system presented here provides the first known solution to digitize and restore deteriorated photographic negatives without damaging the original negative in any way. This thesis work develops new methods of document scanning and restoration suitable for wide-scale deployment. By creating easy to access technologies, library staff can implement their own scanning initiatives and large-scale scanning projects can expand their current document-sets.

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal.

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal.

Le système d'identification automatique (ou système AIS pour automatic identification system) est un système qui permet aux navires et aux stations côtières de s'échanger certaines informations par radio VHF. Ces informations comprennent l'identifiant, le statut, la position, la direction et la vitesse de l'émetteur. L'objectif de cette thèse est de permettre la réception des messages AIS par un satellite en orbite basse sans modifier le matériel existant équipant les navires. Par l'intermédiaire du système AIS, il devient possible de connaitre la position de tous les navires à travers le monde. Plusieurs nouveaux services sont possibles, comme le contrôle maritime global ou, pour les armateurs, la connaissance constante de la position de leurs bateaux. La réception par satellite des signaux AIS est sujette à un niveau de bruit bien plus élevé que lors de la réception de ces signaux au niveau du sol. Ce niveau de bruit rend les méthodes classiques de réception de ces signaux difficilement utilisables. Une première contribution de cette thèse est le développement de nouveaux démodulateurs utilisant des méthodes de correction d'erreurs. Ceux-ci tirent parti de la présence d'un bloc de contrôle de redondance cyclique (CRC) dans les messages ainsi que de certaines informations connues sur la structure des messages et des données. Des adaptations du récepteur proposé ont également été étudiées afin d'intégrer la poursuite de la phase des signaux reçus et de prendre en compte les collisions des messages envoyés simultanément par plusieurs navires. La dernière partie de cette thèse est consacrée à l'étude des méthodes de localisation des navires ne diffusant pas leur position dans leurs messages AIS. Cette localisation tire parti des paramètres des messages reçus tels que le délai de propagation et le décalage en fréquence de la porteuse dû à l'effet Doppler, et d'un modèle de déplacement des navires. / The automatic identification system (AIS) is a system allowing ships and coast stations to exchange some information by VHF radio. This information includes the identifier, status, location, direction and speed of the emitter. The aim of this thesis is to allow the reception of AIS messages by low Earth orbit satellites without modifying the existing ship equipments. With this system, it becomes possible to know the position of all ships over the Earth. As a consequence, several new services become available, such as global traffic monitoring or determining boat location (for ship-owners). Satellite reception of AIS signals is subjected to a higher noise level when compared to ground level reception. This noise makes classical demodulation and decoding methods unusable. A first contribution of this thesis is to develop new demodulators using error correction methods. These demodulators take advantage of the presence of a cyclic redundancy check (CRC) block in the messages as well as known information about the structure of messages and data. Generalizations of the proposed receiver have also been studied in order to take into account the phase noise of the received signals and the possible collision of messages sent simultaneously by several vessels. The last part of this thesis is devoted to the study of localization methods for ships that do not transmit their location in AIS messages. This localization takes advantage of information contained in the received messages such as the propagation delay and the carrier frequency shift due to the Doppler effect, and a ship movement model.