Recently, with advances in CMOS process, the RF receiver which is integrated into the SOC chip can effectively reduce production costs. When designing the wireless receiver, one of the most important technologies is to design channel-selection filter. Typically, the design of the channel-selection filter in multi-standard high-frequency will take up a large chip area and higher power consumption. Therefore, in order to reduce the area and power consumption, this thesis designed a low-power OTA and low-pass filter. This thesis presents a multi-mode wireless communication application in the receiver channel selection filter. This filter is designed to use the fifth-order Butterworth low pass filter, the filter range can be used in Bluetooth, cdma2000, wideband CDMA, and IEEE 802.11a/b/g/n wireless LAN. Using floating transistor architecture in the input stage of OTA can effectively increase the THD performance. Using MOS transistors operating in triode region and combined with current multiplier can achieve the voltage-to-current conversion. Using the trans-linear loop can reach a wide tunable range, and the OTA operating in weak inversion region can significantly reduce the transconductance. Implementation is to use the TSMC 0.18£gm CMOS process. Simulation results show that the successful operation of this filter can be between 650 kHz ~ 22MHz frequency range. The filter may have compatibility in different wireless communication applications. 14.5mW to 17.5mW, respectively, is the smallest to the largest power consumption. The supply voltage is 1.2 volts.