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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Splash-2 shared-memory architecture for supporting high level language compilers

Fross, Bradley K. 14 April 2009 (has links)
Modem computer technology has been evolving for nearly fifty years, and has seen many architectural innovations along the way. One of the latest technologies to come about is the reconfigurable processor-based custom computing machine (CCM). CCMs use field programmable gate arrays (FPGAs) as their processing cores, giving them the flexibility of software systems with performance comparable to that of dedicated custom hardware. Hardware description languages are currently used to program CCMs. However, research is being performed to investigate the use of high-level languages (HLLs), such as the C programming language, to create CCM programs. Many aspects of CCM architectures, such as local memory systems, are not conducive to HLL compiler usage. This thesis proposes and evaluates the use of a shared-memory architecture on a Splash-2 CCM to promote the development and usage of HLL compilers for CCM systems. / Master of Science
2

Simulation of an Implementation and Evaluation of the Layered Radio Architecture

Neel, James O'Daniell 10 January 2003 (has links)
Software radio is a radio that is substantially defined in software and whose physical layer behavior can be significantly altered through changes to its software. As a primary goal of software radio is the ability to support existing and future wireless protocols, software radio necessitates the use of a rapidly reprogrammable baseband processing solution. However third generation wireless protocols represent a significant increase in complexity over second generation protocols. Due to the natural performance sacrifices that must be made when moving an application from an Application Specific Integrated Circuit (ASIC) to a general purpose processor or a digital signal processor, it is feared that reprogrammable processing solutions may not suffice for the emerging wireless protocols, which would significantly hinder the realization of software radio, particularly in the handheld domain where power consumption and chip area are critical. Recently, the Configurable Computing Lab at Virginia Tech developed a new breed of reprogrammable processor which they called "custom computing machine" (CCM). Representing a dramatic departure from traditional architectures used for baseband processing solutions, CCMs utilize a large number of optimized and programmable processing cores connected through a programmable mesh. Due to this architectural approach, CCMs have been promoted as supplying a level of processing power and power efficiency similar to ASICs while providing a level of reconfigurability similar to that of a DSP. Subsequently, Dr. Srikathyayani Srikanteswara proposed a new software radio architecture, known as the Layered Radio Architecture, which is intended to facilitate the inclusion of CCMs into a software radio. The primary goal of the research presented in this thesis is to demonstrate how a particular CCM, Stallion, can be used within the Layered Radio Architecture to provide sufficient processing performance, power efficiency, and reconfigurability to meet the constraints of the handheld domain through implementations of a single user adaptive receiver with adaptive complex filtering and a W-CDMA downlink rake receiver. These metrics are measured from a detailed simulation of Stallion and the Configuration Layer of the Layered Radio Architecture using advanced object oriented programming techniques that facilitate the inclusion of statistics gathering routines into normal operation. To provide perspective, these statistics are compared to the performance that could be expected from an implementation on a top-of-the-line DSP. / Master of Science

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