This paper presents Radix 95n, a binary to text data conversion algorithm. Radix 95n (base 95) is a variable length encoding scheme that offers slightly better efficiency than is available with conventional fixed length encoding procedures. Radix 95n advances previous techniques by allowing a greater pool of 7-bit combinations to be made available for 8-bit data translation. Since 8-bit data (i.e. binary files) can prove to be difficult to transfer over 7-bit networks, the Radix 95n conversion technique provides a way to convert data such as compiled programs or graphic images to printable ASCII characters and allows for their transfer over 7-bit networks.

Intercomputer communications involves the transfer of information between intelligent hosts. Since communication costs are almost proportional to the amount of data transferred, the processing capability of the respective hosts might advantageously be applied through pre-processing and post-processing of data to reduce redundancy. The major emphasis of this research is development of the Substitution Method which minimizes data transfer between hosts required to reconstruct user JCL files, Fortran source files, and data files. The technique requires that a set of user files for each category of files be examined to determine the frequency distribution of symbols, fixed strings, and repeated symbol strings to determine symbol and structural redundancy. Information gathered during the examination of these files when combined with the user created Source Language Syntax Table generate Encoding/Decoding Tables which are used to reduce both symbol and structural redundancy. The Encoding/Decoding Tables allow frequently encountered strings to be represented by only one or two symbols through the utilization of table shift symbols. The table shift symbols allow less frequently encountered symbols of the original alphabet to be represented as an entry in a Secondary Encoding/Decoding Table. A technique is described which enables a programmer to easily modify his Fortran program such that he can take advantage of the Substitution Method's ability to compress data files by removing both informational and structural redundancy. Each user file requested to be transferred is preprocessed at cost, C[prep], to reduce data (both symbol and structural redundancy) which need not be transferred for faithful reproduction of the file. The file is transferred over a noiseless channel at cost, C[ptran]. The channel consists of presently available or proposed services of the common-carriers and specialized common-carriers. The received file is post-processed to reconstruct the original source file at cost, C[post]. The costs associated with pre-processing, transferring, and post-processing are compared with the cost, C[otran], of transferring the entire file in its original form. / Ph. D.

No description available.

In recent years, chemical instrumentation has become much more sophisticated. Most analytical equipment now incorporates a microprocessor or is interfaced to a microcomputer. As a result, chemists can collect an immense amount of data on a single sample in a short period of time. While there may be an advantage to gathering such a great deal of information, problems can arise from too much information. Today, analysts commonly are faced with the dual problems of storing and analyzing the resulting flood of information. The goal of this research has been to address the problems of data storage and data analysis. Specifically, data compression techniques and spectral search and match algorithms have been developed. The data compression techniques developed utilize the Hadamard Transform and the modified zero-crossing clipping algorithm. The spectral search technique utilizes the unique format of the compressed and clipped data to greatly accelerate spectrum identification. To demonstrate the feasibility of this technique, three-dimensional fluorescence spectra of polynuclear aromatic compounds have been used. The results indicate data compression techniques and the application of these techniques to a library search system for three-dimensional fluorescence spectroscopy were both successful. / Ph. D.

Scientific computing and machine learning are two major areas for modern computing demands. The former has applications in physics simulation and mathematical modeling while the latter has become the mainstream approach for tasks such as image classification and natural language processing. Despite the seemingly disparate application domains, the two types of workloads are essentially similar to each other in that their dominant computing kernels are both sparse/dense matrix-vector multiplications. Moreover, conventional computing platforms for these workloads - multicore CPUs/GPUs and microprocessors, consume a large amount of energy and/or in many cases still lack in performance for either cloud or edge applications. Therefore, it is an essential task to develop custom hardware accelerators that improve the energy efficiency and performance and alleviate the performance bottlenecks in CPUs/GPUs. Toward this goal, the thesis presents four hardware accelerator/architecture designs demonstrating significant improvements in key metrics over prior art. The first design is a novel solver chip for partial differential equations (PDEs), a critical mathematical model in scientific computing. Prototyped in 65 nm, the chip features a programmable floating-point processor array architecture. It dramatically improves the range of mappable problems and the solution precision compared to prior art while being 40x faster under the same energy-delay product. The second design, which is part of a system on a chip (SoC) manufactured in 28 nm, is an accelerator for the inference process of convolutional neural networks (CNNs), a popular type of neural network model in machine learning. It incorporates digital in-memory computing modules to efficiently execute the matrix-vector multiplication operations. The resulting SoC achieves 88x higher energy-delay product than prior art. The third design aims to improve the energy efficiency of sparse matrix-vector multiplication (SpMV) by reducing off-chip data movement. Using the gzip compression algorithm, the design offline compresses matrix data in off-chip memory while decompressing it on the fly during computation runtime using custom on-chip decompression hardware. Prototyped in 28 nm, the chip achieves 2.32x system-level energy efficiency improvement over prior art. The fourth design applies the on-the-fly gzip decompression to commercial GPU platforms, aiming at expanding the effective off-chip memory bandwidth. The design proposes a compressed block cache prefetching scheme to address the critical challenges of using gzip for memory decompression purposes in GPUs. Evaluated using open-source simulators, the design achieves 5.3-20.3% performance improvements over the baseline model.

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1977 / Vita. / Includes bibliographical references. / Ph. D. / Ph. D. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science

Thesis--Technische Universität Hannover. / Includes bibliographical references.

Thesis (Ph. D.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Thesis (M.S.) -- Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at El Paso, 2007. / Title from title screen. Vita. CD-ROM. Includes bibliographical references. Also available online.