Thesis (M.S.)--Brigham Young University. Dept. of Computer Science, 2004. / Includes bibliographical references (p. 47-48).

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Hsien-Hsin S. Lee. / Includes bibliographical references (leaves 55-58).

Thesis (M.Phil.)--City University of Hong Kong, 2009. / "Submitted to Department of Computer Science in partial fulfillment of the requirements for the degree of Master of Philosophy." Includes bibliographical references (leaves 103-108)

Thesis (M.Eng.)--Memorial University of Newfoundland, 2002. / Bibliography: leaves 143-152.

Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references (leaves 163-178). Also available in electronic version. Access restricted to campus users.

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2003. / Vita. Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Thesis (M.S.)--Brigham Young University. Dept. of Computer Science, 2003. / Includes bibliographical references (p. 51-54).

No description available.

A new multiplier that supports fields GF(p) and GF (2n) for the public-key cryptography, and fields GF (28) for the secret-key cryptography is proposed in this thesis. Based on the core multiplier and other extracted common operations, a novel hybrid crypto-processor is built which processes both public-key and secret-key cryptosystems. The corresponding instruction set is also presented. Three cryptographic algorithms: the Elliptic Curve Cryptography (ECC), AES and RC5 are focused to run in the processor. To compute scalar multiplication kP efficiently, a blend of efficient algorthms on elliptic curves and coordinates selections and of hardware architecture that supports arithmetic operations on finite fields is requried. The Nonadjacent Form (NAF) of k is used in Jacobian projective coordinates over GF(p); Montgomery scalar multiplication is utilized in projective coordinates over GF(2n). The dual-field multiplier is used to support multiplications over GF(p) and GF(2n) according to multiple-precision Montgomery multiplications algorithms. The design ideas of AES and RC5 are also described. The proposed hybrid crypto-processor increases the flexibility of security schemes and reduces the total cost of cryptosystems. / viii, 87 leaves : ill. (some col.) ; 28 cm.

A new 32-bit reconfigurable FPGA implementation of AES algorithm is presented in this thesis. It employs a single round architecture to minimize the hardware cost. The combinational logic implementation of S-Box ensures the suitability for non-Block RAMs (BRAMs) FPGA devices. Fully composite field GF((24)2) based encryption and keyschedule lead to the lower hardware complexity and convenience for the efficient subpipelining. For the first time, a subpipelined on-the-fly keyschedule over composite field GF((24)2) is applied for the all standard key sizes (128-, 192-, 256-bit). The proposed architecture achieves a throughput of 805.82Mbits/s using 523 slices with a ratio throughput/slice of 1.54Mbps/Slice on Xilinx Virtex2 XC2V2000 ff896 device. / ix, 77 leaves : ill. ; 29 cm.