This thesis presents the design and implementation of the pipeline architecture of H.264/AVC video decoder. The H.264 video compression standard is one of the emerging standards proposed by Joint Video Team (JVT), which can provide high compression ratio and good rate distortion efficiency. It adopts smaller block size and finer motion vector resolution to achieve better predicted motion compensated pictures. While the compression ratio is greatly improved, the computational complexity also increases a lot. How to design the efficient H.264 decoder has become an important topic. This thesis first addresses the design issue of the individual module, and several good architectural solutions are proposed. For the design of the interpolation module, a novel interpolator architecture which can dynamically configure the datapath to perform different computation schedules suitable for the input order of reference samples is proposed. The resulted architecture not only reduces the hardware requirement, but most importantly the communication time spent to move the reference data can be overlapped with the computation time of the predicted samples. Our experimental result shows that the proposed interpolator can achieve 40% average cycle reduction with less hardware cost. For the design of deblocking filter, the thesis also proposes a novel schedule which interleaves the operation of row and column filtering that can lead to a low-cost deblocking filter based on the single-port memory. For the design of variable length decoder, this thesis proposes a new table partitioning method to reduce the overall table size. Finally, all the individual modules are further integrated in the pipelining fashion to increase the overall decoding throughput. The minimum pipelining unit between different stages used in the proposed decoder is the 4x4 block such the memory buffer required can be greatly reduced. The proposed architecture can perform the real-time decoding of video at the resolution of 640x480 pixels.