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The continuing of industrial revaluation and capitalism today are facing the most difficult enemy ever. 38 billion years of natural resources will be destroyed and over utilized within the next 10 years. The global business will be paying 1500 billion dollars to overcome the effect of changing wheather and natural environment especially those digital industry. The global high tech industry is having a ¡§Green colour¡¨ hits. It is not a war in invoice competition. It is a war for life. The continues of the technological advantages and fast development in industry, have bringing in a convenient life to human being but on the other hand it had introduced lots of troubles in our natural environment. The awareness of our natural environment began in 1970, the first ¡§Global Day¡¨ continues in 1972, Stockholm¡¦s environment and development conference, people begins their awareness of our natural environment, knowledge, understanding and its trouble. In August this year the European alliances will be announcing the three directions of the law in the waste of electrical engineering and facility and electrical facility and products awareness. Therefore the producers have to register their product before August this year. Which includes the digital produce company, products, after sales services and recycling business are all effected bye the law. The following trend of Green Process will be the next demand on industry generation. Under the green process direction, every products that produced have to be recyclable, Lead free, Halogen free . Therefore the trend will bring to a whole new revolution of digital industry. Taiwan¡¦s IC packing industry is one of the most important rule to be a part in global semiconductor. In order to be part of trend, and facing the changing environment, follow the flow is the only way to continue the business. Our aim for this research is to discover the green products¡¦ that¡¦s affect to the packing industry. Our research is hoping to discover a deep underneath for every cases of green process products changing and to the IC packing industry. We also hoping the research could analyze the future development of the green process environment.

The thesis considers an understudied form of third party peacemaking, namely peacemaking interventions with kin-state involvement. The main research question this thesis seeks to analyse is how local actors, their kin-states and third party peacemakers interact within the context of a peacemaking intervention for power-sharing in deeply divided societies. The literature on third party peacemaking largely neglects the role of kin-states in peacemaking, while in the literature on power-sharing the role of external actors, including kin-states, remains understudied. This thesis aims to address these gaps by investigating the recent peacemaking interventions for power-sharing with kin-state involvement in Cyprus, Bosnia and Northern Ireland. The findings of the case studies are combined and assessed through the use of a five-level analytical framework, which includes the local actors level; the local actors-third party peacemaker level; the local actors-kin-state(s) level; the third party peacemaker-kin-state(s) level; and the kin-states level. The analysis identifies a number of conditions pertinent to each of these levels which affect peacemaking interventions for power-sharing in deeply divided societies with kin-state involvement. There are two main original contributions of this thesis to the above mentioned literatures. First, it proposes a typology of kin-state involvement in peacemaking, which categorises kin-state involvement into four roles: promoter; quasi-mediator; power-broker; and enforcer. Second, through the use of game theoretical analysis, more specifically a nested games approach, it illustrates how the interaction between local actors, their kin-states and third party peacemakers can be modelled in the context of a peacemaking intervention for power-sharing. The empirical and theoretical conclusions of this study indicate that kin-state involvement in third peacemaking interventions is more complex and fluid than widely assumed.

This study uses the current laws and regulations of Mainland China as the researching objectives trying to figure out some possible methods to be the references for those who are interested in investing into Chinese market in the near future. Although PRC has agreed to release trading right after joined WTO, the detailed regulations are not very clear yet. For those foreign traders may uncarefully disobey China¡¦s laws due to misunderstand the laws or just believe people¡¦s words in the market. This may put themselves in a high risk situation. After analyzes the laws, this study designs a suitable open questionnaire to have in-depth interviews with some high level managers currently working in Mainland China to explore Taiwanese SME¡¦s activities. On the method of qualitative research, we have to concern on three creteria: A. correct description, B.criticism and analysis, C. discovery¡CThis study found: information is difficult to be collected in China market¡Bthe credit is poor of your business objects¡Bchannels and sources of goods are difficult to control and difficulty to collect money. These problems will increase the transaction cost. While to build Guangxi or relationship and establish commercial friendship in Chinese market will help you to reduce the transaction cost. China market is a rapid growing but also high competitive market. To find a proper entry model is very important topic.

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O trabalho propõe um circuito para caracterização estatística do fenômeno Bias Temperature Instability (BTI). O circuito tem como base uma matriz de transistores para caracterização eficiente em larga escala de BTI. O design proposto visa o estudo da variabilidade de BTI dependente do tempo em dispositivos altamente miniaturizados. Para tanto se necessita medir centenas de dispositivos, a fim de se obter uma amostra estatisticamente significante. Uma vez que variações nos tempos de estresse e medida dos dispositivos podem gerar erros no processo de caracterização, o circuito implementa em chip (on-chip) o controle dos tempos de estresse e de medida, para que ocorra uma caracterização estatística precisa. O circuito de controle implementado faz com que todos dispositivos testados tenham os mesmos tempos de estresse e os mesmos tempos de recuperação (relaxamento). Desta forma, o circuito proposto melhora significantemente tanto a área utilizada quanto o tempo de medida, quando comparado a alternativas anteriormente implementadas. O leiaute do circuito foi realizado no novo nó tecnológico de 28 nanômetros do IMEC. / This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be electrically characterized in order to obtain a statistically significant sample size. The circuit controls stress and measurement times for accurate statistical characterization, making sure all the devices characterized have the same stress and recovery times. It significantly improves both area and measurement time. The circuit layout is laid out in the new 28nm node IMEC technology.

O trabalho propõe um circuito para caracterização estatística do fenômeno Bias Temperature Instability (BTI). O circuito tem como base uma matriz de transistores para caracterização eficiente em larga escala de BTI. O design proposto visa o estudo da variabilidade de BTI dependente do tempo em dispositivos altamente miniaturizados. Para tanto se necessita medir centenas de dispositivos, a fim de se obter uma amostra estatisticamente significante. Uma vez que variações nos tempos de estresse e medida dos dispositivos podem gerar erros no processo de caracterização, o circuito implementa em chip (on-chip) o controle dos tempos de estresse e de medida, para que ocorra uma caracterização estatística precisa. O circuito de controle implementado faz com que todos dispositivos testados tenham os mesmos tempos de estresse e os mesmos tempos de recuperação (relaxamento). Desta forma, o circuito proposto melhora significantemente tanto a área utilizada quanto o tempo de medida, quando comparado a alternativas anteriormente implementadas. O leiaute do circuito foi realizado no novo nó tecnológico de 28 nanômetros do IMEC. / This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be electrically characterized in order to obtain a statistically significant sample size. The circuit controls stress and measurement times for accurate statistical characterization, making sure all the devices characterized have the same stress and recovery times. It significantly improves both area and measurement time. The circuit layout is laid out in the new 28nm node IMEC technology.

O trabalho propõe um circuito para caracterização estatística do fenômeno Bias Temperature Instability (BTI). O circuito tem como base uma matriz de transistores para caracterização eficiente em larga escala de BTI. O design proposto visa o estudo da variabilidade de BTI dependente do tempo em dispositivos altamente miniaturizados. Para tanto se necessita medir centenas de dispositivos, a fim de se obter uma amostra estatisticamente significante. Uma vez que variações nos tempos de estresse e medida dos dispositivos podem gerar erros no processo de caracterização, o circuito implementa em chip (on-chip) o controle dos tempos de estresse e de medida, para que ocorra uma caracterização estatística precisa. O circuito de controle implementado faz com que todos dispositivos testados tenham os mesmos tempos de estresse e os mesmos tempos de recuperação (relaxamento). Desta forma, o circuito proposto melhora significantemente tanto a área utilizada quanto o tempo de medida, quando comparado a alternativas anteriormente implementadas. O leiaute do circuito foi realizado no novo nó tecnológico de 28 nanômetros do IMEC. / This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be electrically characterized in order to obtain a statistically significant sample size. The circuit controls stress and measurement times for accurate statistical characterization, making sure all the devices characterized have the same stress and recovery times. It significantly improves both area and measurement time. The circuit layout is laid out in the new 28nm node IMEC technology.

No description available.