Emerging electronic system architectures follow increasingly 3D integration concepts driven by further miniaturization, increase of performance, decrease of energy consumption, and implementation of further functionality. Following this More than Moore path, trendsetting on-top-of-complementary metal-oxide semiconductor (CMOS) technologies for nanodevices find increasing attention in semiconductor development roadmaps. Nanodevices implemented through nanomaterials such as semiconducting single-walled carbon nanotubes (CNTs) with their proceeded technology readiness level, give additional degree of freedom to upgrade such systems as substrate-independent and post-CMOS compatible technologies are already available. Although, they inherently feature extraordinary properties several technological obstacles are not yet addressed. Pronounced obstacles like inadequate CNT assembly structure, interfering parasitic effects related to CNT/substrate interfaces, as well as insufficient pre-stress state of the CNTs are tackled within this thesis aiming on CNT-based piezoresistive sensors. Following a holistic approach, the activities range from the implementation of chromatography-based length separation of CNTs over wafer-level micro- and nanotechnological process-, module-, and equipment developments towards comprehensive and statistical data analysis. It could be shown, that short CNTs adversely affect integrability and reproducibility, underlined by a 25% decline of the fabrication yield of CNT based field-effect transistors (CNT-FETs) with respect to long CNTs. It furthermore turns out, that performance of CNT-FETs built from long CNTs show significant benefits in terms of subthreshold swing (up to 163%) and hole mobility (up to 300%), which could be explained by suppressed CNT chain formation within the transistor channel. Furthermore, short-channel piezoresistive CNT sensors in FET configuration show a significant drain-induced barrier thinning characterized by a degradation of the subthreshold swing and a threshold voltage roll-off of (−1370± 130) mV · V−1 upon applied drain-source voltage. This device-specific effect enhances the intrinsic strain-sensitivity of the sensor of up to 150% with a maximum measured gauge factor of 800. In this regard, supporting transport simulations underline the importance of the Schottky barrier at the source/CNT junction as the dominating junction for tunneling currents responsible for the gained enhancement. Finally, a technology module was developed, which further reduce parasitic effects such as stick-slip and slack behavior of device-integrated CNTs upon mechanical load by incorporation of layout-determined pre-strain. Utilizing a post-CMOS compatible sacrificial layer approach combined with residual stressed membranes, the integrated CNTs were strained by almost 1% in axial direction. This consequences in an reduced sensor offset determined by a reduction of the detection limit to 30 MPa. In addition this modul was successfully implemented by heterogeneous on-top-of application-specific integrated circuit technologies where CNT-FETs were characterized over an embedded complementary metal-oxide semiconductor multiplexer circuit. Hence, this work displays novelty and provides significant contributions on heterointegrated system-on-chip applications of upcoming nanomaterial-based devices for environmental sensing, condition monitoring, photonic integrated circuits, up to promising architectures for neuromorphic computing and the quantum technology science and application.