Tang Tze Yeung Eric. / Thesis submitted in: July 2003. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 69-75). / Abstracts in English and Chinese. / ABSTRACT --- p.II / ACKNOWLEDGMENT --- p.II / Chapter 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Embedded System --- p.1 / Chapter 1.2 --- Embedded Processor --- p.1 / Chapter 1.3 --- Embedded System Design --- p.3 / Chapter 1.3.1 --- Current Embedded System Design Challenges --- p.3 / Chapter 1.3.2 --- Embedded System Design Trend --- p.4 / Chapter 1.4 --- Efficient Software Development for Microprocessor --- p.8 / Chapter 1.4.1 --- Efficient Software Development Methodology --- p.8 / Chapter 1.5 --- Thesis Organization --- p.10 / Chapter 2 --- SOURCE CODE OPTIMIZATION --- p.11 / Chapter 2.1 --- Source Code Optimization Strategy --- p.11 / Chapter 2.2 --- Source Code Transformations --- p.12 / Chapter 2.2.1 --- Strength Reduction --- p.12 / Chapter 2.2.2 --- Function Inlining --- p.13 / Chapter 2.2.3 --- Table Lookup --- p.13 / Chapter 2.2.4 --- Loop Transformations --- p.13 / Chapter 2.2.5 --- Software Pipelining --- p.15 / Chapter 2.2.6 --- Register Allocation --- p.17 / Chapter 2.3 --- Case Study: Source Code Optimization on the StrongARM (SA1110) Platform --- p.18 / Chapter 2.3.1 --- StrongARM architecture --- p.18 / Chapter 2.3.2 --- StrongARM pipeline hazard illustration --- p.20 / Chapter 2.3.3 --- Source Code Optimization on StrongARM --- p.21 / Chapter 2.3.4 --- Instruction Set Optimization of StrongARM --- p.27 / Chapter 2.4 --- Conclusion --- p.32 / Chapter 3 --- FLOAT-TO-FIXED OPTIMIZATION --- p.33 / Chapter 3.1 --- Introduction to Fixed-point --- p.34 / Chapter 3.1.1 --- Fixed-point representation --- p.34 / Chapter 3.1.2 --- Fixed-point implementation --- p.35 / Chapter 3.1.3 --- Mathematical functions implementation --- p.38 / Chapter 3.2 --- Case Study: Fingerprint Minutiae Extraction Algorithms on the Strong ARM platform --- p.41 / Chapter 3.2.1 --- Fingerprint Verification Overview --- p.42 / Chapter 3.2.2 --- Fixed-point Implementation of Fingerprint Minutiae Extraction Algorithm --- p.49 / Chapter 3.2.3 --- Experimental Results --- p.51 / Chapter 3.3 --- Conclusion --- p.56 / Chapter 4 --- DOMAIN SPECIFIC OPTIMIZATION --- p.57 / Chapter 4.1 --- Case Study: Font Rasterization on the Strong ARM platform --- p.57 / Chapter 4.1.1 --- Outline Font --- p.57 / Chapter 4.1.2 --- Font Rasterization --- p.59 / Chapter 4.1.3 --- Experiments --- p.63 / Chapter 4.2 --- Conclusion --- p.66 / Chapter 5 --- CONCLUSION --- p.67 / BIBLIOGRAPHY --- p.69

Lee Ming Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 78-80). / Abstracts in English and Chinese. / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1. --- Background on development of AA size micro power generator --- p.1 / Chapter 1.1.1. --- Brief introduction --- p.1 / Chapter 1.1.2. --- Proposed micro power generator for wireless applications --- p.2 / Chapter 1.2. --- Literature survey --- p.3 / Chapter 1.2.1. --- Comparison of other energy sources --- p.3 / Chapter 1.2.2. --- An overview of research on electromagnetic micro power generator --- p.5 / Chapter Chapter 2 --- Principle of Micro Power Generator --- p.7 / Chapter 2.1 --- Design objective ofAA size micro power generator --- p.7 / Chapter 2.2 --- Faraday ´ةs Law of induced current --- p.9 / Chapter 2.3 --- Modal for the micro power generator system --- p.10 / Chapter 2.4 --- Design of the micro power generator --- p.13 / Chapter 2.5 --- Integrated power cell --- p.20 / Chapter Chapter 3 --- MEMS Resonator --- p.23 / Chapter 3.1. --- Design of the micro resonator --- p.23 / Chapter 3.1.1. --- Introduction to micro resonator --- p.23 / Chapter 3.1.2. --- Selection of material --- p.24 / Chapter 3.1.3. --- Different modes of vibration --- p.25 / Chapter 3.2. --- Laser Micro-machining --- p.26 / Chapter 3.3. --- MEMS Fabricated Spring --- p.28 / Chapter 3.3.1. --- Introduction of SU-8 based electroplating technique --- p.28 / Chapter 3.3.2. --- Fabrication process --- p.31 / Chapter Chapter 4 --- Characteristic of AA Size Micro Power Generator --- p.33 / Chapter 4.1. --- Experiment on a single micro power transducer --- p.36 / Chapter 4.1.1. --- Testing a single transducer without loading --- p.37 / Chapter 4.1.2. --- Testing a single transducer connected with a power management circuit --- p.38 / Chapter 4.1.3. --- Testing a single transducer with power management circuit and a 100kΩ resistor --- p.39 / Chapter 4.1.4. --- Summary of experiments on the micro power transducer --- p.40 / Chapter 4.2. --- Experiment on finding a way to increase power output --- p.41 / Chapter 4.3. --- Experiment for connecting two micro power transducers --- p.43 / Chapter 4.3.1. --- Testing on two micro power transducers connected in series --- p.44 / Chapter 4.3.2. --- Testing on combined micro power transducers with power management circuit --- p.47 / Chapter 4.4. --- Experiment on the integrated AA size micro power generator --- p.49 / Chapter 4.4.1. --- Interaction of magnetic dipole between two micro power transducers --- p.50 / Chapter 4.4.2. --- AA size micro power generator under varying input vibration frequencies --- p.52 / Chapter Chapter 5 --- Simulation and Analysis --- p.55 / Chapter 5.1. --- FEA Modeling of the MEMS Resonators --- p.55 / Chapter 5.2. --- Micro power generator system modeling --- p.57 / Chapter 5.3. --- Optimization --- p.60 / Chapter Chapter 6 --- Applications --- p.63 / Chapter 6.1. --- Wireless Temperature Sensing System --- p.64 / Chapter 6.2. --- Measurement of car vibration for noval applications --- p.70 / Chapter 6.2.1. --- Measurement of car vibration in stationary condition --- p.71 / Chapter 6.2.2. --- Measurement of car vibration traveling in The Chinese University of Hong Kong (CUHK) --- p.72 / Chapter 6.2.3. --- Measurement of car vibration traveling in rough pattern road (Tai Po Road) --- p.73 / Chapter 6.3. --- Human motion analysis --- p.74 / Chapter Chapter 7 --- Conclusion --- p.76 / Reference --- p.78 / Appendix --- p.81

隨著工藝尺寸的縮小，集成電路的時序行為變得越來越難以預測，某原因在於各種偏差效應，比如製造偏差、供電電壓波動以及溫度變化。對於傳統的“確保正確“的設計方式，我們需要留出很大的餘量，這就減少了工藝進步帶來的好處。時序監測C Timing Speculation) 因為具有錯誤檢測和更正機制而成為一種很有前景的解決辦法。採用這種方式，電路可以工作在有不太頻繁時序錯誤的情況下。而對於這種時序監視的設計方式，現有的優化方法大多主要是在電路結構確定之後的一些小的改動。因為這些方法無法對電路結構進行改變，所以它們的效果很有限。因此，我們在這篇論文里提出了在電路綜合(synthesis)過程中的一些優化方法，這些方法是能夠改變電路結構的。我們提出的優化方法主要集中在優化電路的硬件開銷和電路性能的方面。我們提出的方法主要包括兩個設計階段。 / 第一個階段是在邏輯綜合(Logic synthesis) 的時候.在邏輯綜合的時候，我們有很大的自由度去根據時序監測的特性來改變電路的結構。如果結合了特殊的實現方法，電路出現時序錯誤的頻率就會得到降低，從而提高了電路的性能。 / 第二個階段是在邏輯綜合之後的后綜合(Post-synthesis) 階段。為了減少時序監測的硬件上的開銷，我們提出了基於retiming 手法的再綜合(resynthesis) 方法.這種方法可以減少可疑寄存器(suspicious FF) 的數量從而降低硬件開銷。另外這種辦法也可以提高電路的吞吐量(throughput) 。為了進一步對電路進行優化，我們挨著又提出了基於rewiring 手法的電路吞吐量優化方法。此外，利用這種方法我們還可以消除部份電路里的短通路(short path) 從而進一步減少電路的硬件開銷。在這個階段，我們仍然具有改變電路結構的靈活性，因此我們的方法具有很好的效果。 / With technology scaling, the timing behavior of integrated circuits (ICs) becomes more unpredictable due to various variation effects, such as manufacturing variability, voltage fluctuations and temperature changes. A large design guard band is therefore reserved to ensure “always correct“ operation for traditional designs, disminishing the benefits of technology scaling. Timing speculation with error detection and correction mechanisms is a promising solution to tackle the above problem. With this technique, circuit can work under infrequent timing errors. The existing optimization techniques for timing speculated circuits are mainly based on some small modifications after the circuit structure is determined. Without the ability to change circuit structure, the efficiency is limited. Therefore, in this thesis we propose optimization techniques during the process of synthesis so that the flexibility is provided to make circuit structural change. Our optimization fo¬cuses on hardware cost and circuit performance and the proposed techniques are included in two design steps. / First step is logic synthesis. During the process of logic synthesis, there is large flexibility to change the circuit structure by considering the features of timing speculation. With intentional strategy the timing error probability can be reduced so as to improve the circuit throughput. / Second step is post-synthesis techniques after logic synthesis. To reduce the hardware cost for timing speculation, we propose a re-synthesis method based on the idea of retiming to reduce the number of suspicious FFs where timing errors mainly happen. This technique can also help to improve the circuit throughput if carefully implemented. To further improve the throughput, we also propose to use rewiring technique which is also called redundancy addition and removal (RAR) to optimize circuit for throughput. Furthermore, this technique can also be used to break down short paths so as to save the hardware cost. During this step, flexibility is also provided to make circuit structural change so that the efficiency is guaranteed. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Liu, Yuxi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 70-76). / Abstracts also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Timing Speculation --- p.1 / Chapter 1.1.1 --- Circuit Timing Problem --- p.1 / Chapter 1.1.2 --- Possible Solution --- p.3 / Chapter 1.1.3 --- Timing Speculation is Promising --- p.4 / Chapter 1.1.4 --- Razor Flip-flop --- p.5 / Chapter 1.2 --- Problems for Timing Speculation --- p.6 / Chapter 1.2.1 --- Hardware Cost of Timing Speculation --- p.7 / Chapter 1.2.2 --- Performance of Timing Speculation --- p.8 / Chapter 1.3 --- Thesis Motivation and Organization --- p.9 / Chapter 1.4 --- Thesis Contributions --- p.11 / Chapter 2 --- Logic Synthesis for Timing Speculation --- p.13 / Chapter 2.1 --- Introduction --- p.13 / Chapter 2.2 --- Preliminaries --- p.14 / Chapter 2.2.1 --- Timing Speculation --- p.14 / Chapter 2.2.2 --- AIG-Based Logic Synthesis --- p.15 / Chapter 2.3 --- Logic Synthesis for Timing Speculation --- p.16 / Chapter 2.3.1 --- Proposed Optimization Metric --- p.17 / Chapter 2.3.2 --- Proposed Logic Synthesis Solution --- p.19 / Chapter 2.4 --- Experimental Results --- p.24 / Chapter 2.4.1 --- Experimental Setup --- p.24 / Chapter 2.4.2 --- Results and Discussion --- p.25 / Chapter 2.5 --- Conclusion --- p.30 / Chapter 3 --- Post-Synthesis Optimization for Timing Speculation --- p.31 / Chapter 3.1 --- Optimization for Timing Speculation by Retiming --- p.32 / Chapter 3.1.1 --- Introduction --- p.32 / Chapter 3.1.2 --- Preliminaries and Motivation --- p.33 / Chapter 3.1.3 --- Reducing Suspicious FFs by Retiming --- p.35 / Chapter 3.1.4 --- Reducing Timing Error Probability by Retiming --- p.41 / Chapter 3.1.5 --- Padding Short Paths --- p.43 / Chapter 3.2 --- Optimization for Timing Speculation by Rewiring --- p.47 / Chapter 3.2.1 --- Introduction --- p.47 / Chapter 3.2.2 --- Preliminaries --- p.48 / Chapter 3.2.3 --- Timing Optimization by Rewiring --- p.52 / Chapter 3.2.4 --- Reduce Hardware Cost by Rewiring --- p.60 / Chapter 3.3 --- Experimental Results --- p.62 / Chapter 3.4 --- Conclusion --- p.66 / Chapter 4 --- Conclusion --- p.68 / Bibliography --- p.76

最近社會對計算密集型應用程序和高性能的多核計算系統的研究興趣增加。隨著每片芯片和計算資源的核心數量不斷增長的趨勢，更好的金屬互連或其他替代是至關重要的。這亦要滿足高帶寬，低功耗，細小體積和高擴展性的要求。ITRS的報告指出，兼容CMOS的矽光子光互連是一種替代，它符合上述要求，包括體積細少和只需納秒的開關時間，所以矽微環諧振器是具潛能被用為2×2開關元件來建立大規模集成光互連。 / 然而，微環互連的可擴展性可能受限制的，其中四個關注點包括總功耗，插入損耗，光功率不均勻和總串擾。2×2切換微環需要一定的功耗，而插入損耗也限制了每條切換路徑所經過的開關元件的數量。換句話說，開關元件在交互/直行狀態下的非相等損失限制了光互連的可擴展性。此外，在考慮滿足大型光互連的要求，光功率的不均勻性是一個重要的問題。最後，在每個2×2開關元件，輸出光功率洩漏對大型的光互連的輸出造成許多可能的串擾。這在輸出端口的總串擾是十分嚴重，它會減少微環互連的可擴展性。因此，本論文的目的著重於降低整體功耗，路徑的總插入損耗，每個輸出端口的光功率不均勻和每個輸出端口的總串擾。 / 在這篇論文中，我們首先回顧微環諧振器的結構和微環互連的背景。限制互連的可擴展性也將被討論。然後，我們將回顧以前的研究，致力於解決可擴展性問題。通過利用微環開關元件的不相等特徵，我們提出一個有效的模型以找到最佳的開關配置，來減少總功耗和每通道的平均插入損耗。此外，我們還提出一個快速的算法，以較短的計算時間減少交叉狀態開關元件數量。 / There is an increasing research interest on networks-on-chip architectures for growing computation-intensive applications and high-performance multi-core computing systems recently. With the growing trend of number of cores per chip and computation resources per chip, the advancement for conventional interconnections is essential to meet the demands of high-bandwidth capacity, low power consumption, compact footprint and high scalability. A report from ITRS pointed out that optical interconnections based on Complementary Metal Oxide Semiconductor (CMOS)-compatible silicon photonics is an alternative to conform to the above requirements. The carrier-injection-based silicon microring resonators is a promising candidate to build large-scale-integrated optical interconnections using 2×2 switching elements due to its very compact footprint and potential sub-nanosecond switching time. / However, the scalability of microring-based interconnection is limited by issues including power consumption, insertion loss, nonuniformity and crosstalk. Current technology for a 2×2 switching elements of microring requires non-negligible power consumption at cross/bar states on average. Intrinsic insertion loss also limits the number of successive switching elements per switching path. In other words, asymmetric loss characteristics of switching elements limit the scalability of optical interconnections. Also, the nonuniformity of optical power is an important issue to be considered in meeting the requirement of a large-scale optical interconnection. Last, as in each 2×2 switching element, there is an optical power leakage to the non-intended output-port and thus it creates many possible crosstalk powers at each output-port. This total crosstalk at output is severe and needs to be reduced for the scalability consideration of microring-based interconnection. Hence, the aim of this thesis focuses on the reduction in overall power consumption, average total insertion loss per path, average nonuniformity of optical power and total crosstalk at each output-port. / In this thesis we firstly review the background of microring resonator architecture and microring-based interconnections. The severe asymmetric behaviors limiting the scalability of interconnection are discussed. Then we review previous work dedicated to the scalability issues. By leveraging the asymmetric characteristics at cross/bar states of microring switching elements, we then propose an efficient model to find the optimum switching configuration for minimizing the total power consumption and the average insertion loss per path. Heuristics is also proposed to minimize the number of cross state switching elements with a shorter computation time. The results depict that the optimum average total insertion loss per path using 2B-SE achieve a 3.65-dB improvement for 128×128 switch size. The optimum average total insertion loss using 2B-SE in the worst-cast path is shown to be 7.2 dB less than the baseline values without optimization. Furthermore, simulation results show that regarding the nonuniformity in the worst case of the worst case, with the optimum switching configuration, the best improvement is 9.6 dB; the average improvement is 8.7 dB and the least improvement is 7.2 dB for 128×128 switch size. On the other hand, for the total crosstalk per path, simulation results show that the optimum switching configuration can achieve a 1.87-dB improvement for 128×128 switch size on average, compared with the average case without optimization. Also, the total crosstalk has a 2.43-dB improvement for 128×128 switch size in the worst case. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Yuen, Piu Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 48-51). / Abstracts also in Chinese. / Acknowledgement --- p.i / Abstract --- p.ii / 摘要 --- p.iv / Table of Contents --- p.vi / Table of Figures --- p.viii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Overview of microring resonators and microring-based optical interconnection --- p.2 / Chapter 1.3 --- Asymmetric characteristics of microring switching elements --- p.3 / Chapter 1.4 --- Problem statement --- p.5 / Chapter 1.5 --- Motivation of this thesis --- p.6 / Chapter 1.6 --- Outline of this thesis --- p.7 / Chapter Chapter 2 --- Previous work on optimization of microring-based interconnection --- p.9 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.2 --- A previous scheme for insertion loss reduction --- p.10 / Chapter 2.3 --- A previous scheme for nonuniformity reduction --- p.12 / Chapter 2.4 --- Prior work on power consumption in optical networks --- p.14 / Chapter 2.5 --- Prior work on crosstalk in optical cross-connect networks --- p.16 / Chapter 2.7 --- Summary --- p.17 / Chapter Chapter 3 --- Optimization scheme of microring-based interconnection configurations for reduction of power consumption and insertion loss --- p.19 / Chapter 3.1 --- Introduction --- p.19 / Chapter 3.2 --- Principle of determining the optimum switching configurations --- p.20 / Chapter 3.2.1 --- Calculations of power consumption and insertion loss --- p.23 / Chapter 3.3 --- Heuristic for reduction of power consumption and insertion loss --- p.24 / Chapter 3.4 --- Simulation results and discussion --- p.27 / Chapter 3.5 --- Summary --- p.32 / Chapter Chapter 4 --- Optimization scheme of microring-based interconnection configurations for the reduction of nonuniformity and crosstalk --- p.33 / Chapter 4.1 --- Introduction --- p.33 / Chapter 4.2 --- Principle of determining the optimum switching configurations --- p.34 / Chapter 4.2.1 --- Calculation of nonuniformity --- p.35 / Chapter 4.2.2 --- Calculation of crosstalk --- p.36 / Chapter 4.3 --- Simulation results and discussion --- p.39 / Chapter 4.4 --- Summary --- p.42 / Chapter Chapter 5 --- Conclusion and Future Work --- p.44 / Chapter 5.1 --- Conclusion of this thesis --- p.44 / Chapter 5.2 --- Future work --- p.46 / List of Publications --- p.47 / Bibliography --- p.48

隨著半導體工藝技術的不斷進步 (technology scaling) ，更多的設計資源不得不用於確保集成電路的時序正確性。這種“面向最壞情況(worstcase-oriented) 的芯片設計方法導致了悲觀保守的芯片設計方案，增加了性能及功耗開銷，減少了工藝進步帶來的效益。 / “優於最壞情況(better-than-worst-case) 的芯片設計方法允許犧牲一定的芯片可靠性 (reliability) 來提高性能以及降低功耗，從而提高計算的能量效率 (energy efficiency) 。“優於最壞情況設計方法的核心思想在於放松對芯片可靠性的硬性需求。既然時序錯誤 (timing error) 在關鍵路徑中的發生頻率並不高，我們可以允許錯誤發生，從而節約用於防止錯誤發生所需要的高額開銷。而當錯誤發生時，再利用錯誤檢測和更正方法(error detection and correction) 來消除錯誤造成的影響。這種無須保證計算過程永遠正確無誤的方法通常被稱作“ 時序推測 (timing speculation) 。然而，不幸的是，由於傳統的“面向最壞情況的設計方法往往導致芯片中存在所謂的“關鍵路徑壁壘(wall of critical paths) ，時序推測技術的有效性在一定程度上受限。 / 為了解決上述問題，我們首先研究了時序推測技術的前提與前景，也就是研究了如何估計時序推測技術能夠帶來的最小和最大效益。此外，我們也研究了時序推測芯片 (timing-speculative circuit) 中的若幹設計優化問題。首先，由於引入時序推測技術能夠提高多電壓 (multi-supply voltage)技術的靈活性，我們闡述了時序推測芯片中的多電壓設計問題，並創造性地提出了一種基於動態規劃 (dynamic programming) 的算法來解決這個問題。此外，我們提出了時序推測芯片中的時鐘差異規劃 (clock skew scheduling) 問題。在考慮了時序錯誤率 (timing error rate) 等因素的影響後，我們設計了新穎有效的方法來解決該問題。最後，鑒於工藝差異(process variation) 和老化效應 (wearout effect) 對芯片時序的影響，而且這種影響很難在設計階段被消除，我們提出了一種實時的時序差異調整(clock skew tuning) 架構。利用精心設計的硬件結構，我們可以實時地收集時序錯誤的信息，相應地調整時鐘差異，從而極大地減弱了時序不確定性對芯片性能的影響。 / As circuit non-idealities inevitably worsen with technology scaling, more design resource has to be incorporated to ensure integrated circuit (IC) timing correctness. Such worst-case-oriented design methodology results in pessimistic designs with considerable power and performance overheads, lessening the benefits provided by technology scaling. / Better-than-worst-case (BTWC) design methodology that allows reliability to be traded off against power and performance was proposed to dramatically improve the computation energy-efficiency. The basic idea behind BTWC design methodology is that, since circuit non-idealities mainly manifest themselves as infrequent timing errors on critical paths of the circuit, we can over-clock operating frequency and/or over-scale supply voltage of the chip to a critical point, where timing errors occur, and achieve error-resilient computations by performing timing error detection and correction. This approach is generally referred to as timing speculation, with which it is not necessary to guarantee “always correct operations. Unfortunately, there is usually a “wall of critical paths in the final implementation of a circuit caused by conventional worst-case-oriented design methodology, suggesting that, given a fixed circuit design, the effectiveness of timing speculation is limited by a fixed threshold beyond which the circuit performance/energy efficiency will drop significantly. / To address the above problem, this thesis first proposes to study the premises and prospects of timing speculation by analyzing the minimum and maximum potential benefits that are achievable by timing speculation techniques. After answering the question posed by the conflict between conventional techniques and timing speculation, this thesis investigates multiple design and optimization problems in timing-speculative circuits. Firstly, as introducing timing speculation capability into circuits can naturally extend the flexibility of multi-supply voltage (MSV) designs to a new horizon, this thesis formulates the MSV design problem for timing-speculative circuits and develops a novel algorithm based on dynamic programming to solve it. Secondly, this thesis develops a general formulation of clock skew scheduling (CSS) problem for timing-speculative circuits, wherein timing error rate and its corresponding impact are explicitly considered, and proposes novel algorithms to tackle this problem. Finally, considering the impact of timing uncertainties caused by process variation and wearout effects, which is very difficult to be modeled and addressed at design stage, this thesis also develops a novel online clock skew tuning framework for timing-speculative circuits. By utilizing an elaborately-designed hardware architecture to collect timing error information and tune clock skews at runtime, variation effects can be effectively mitigated. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Ye, Rong. / Thesis (Ph.D.) Chinese University of Hong Kong, 2014. / Includes bibliographical references (leaves 131-142). / Abstracts also in Chinese.

Asynchronous circuits are usually applied for the communications between multiple clock-domain blocks in some SoCs. According to application-specific traffic, efficiently allocating reasonable buffers in an asynchronous NoC router can avoid the waste or shortage of buffer resource. The method of application-specific asynchronous First-In-First-Out buffer allocation can reduce the silicon area and the power consumption to improve the network latency. According to given traffic pattems, the save of area buffer of our buffer-allocation method can be up to near 30% and the latency is reduced a little at same time. / Bypass schemes is efficient to reduce the average propagation cycles in NoCs. We propose novel lookahead bypass scheme to improve the network latency. The lookahead bypass router is implemented and evaluations of valious configurations are compared, where the proposed architecture significantly improves the packet latency up to 32.1 % over a baseline router. These prove that the router can reduce the average network latency and power consumption, and decreases the reliance on large buffers and virtual channels. Furthermore, the application-specific short-circuit channel is introduced to add some short cuts in a router to bypass the crossbar switch. It can provide additional internal channels to bypass the crossbar and increase the total probability of lookahead bypass. Therefore, the latency can be further reduced. And the throughput can be increased in some applications. / Multicast is preferred in parallel computers. It is an inherent fault of network-on-chip as compared with competitor bus architecture. Software method is a conventional method to implement multicast, but there is a large overhead in latency. The latency overhead of a 4-flit multicast packet achieves 6∼7 times as compared with tree-based or path-based hardware multicast. Hardware multicast support is necessary in these applications. A group-based hardware multicast method is desclibed and estimated in this thesis. Quality of service is also introduced to speed up multicast packets. / On-chip communication infrastructures are inunensely important today. As silicon technology allows more than one billion of transistors in a single piece of silicon, the system-on-chip (SoC) circuits can contain already a large number of processing elements (PEs). Therefore, the Networks-on-Chip (NoCs) are a generally accepted concept to solve the problems such as the scalability and throughput limitation, and physical design problems inherent in dedicated links and shared buses. However, the state-of-the-art on-chip network suffers from latency overhead due to the additional network as compared with dedicated wire connection. According to the different application enviromnents, there are different low-latency technologies for networks-on-chip. This thesis proposes some methods for low-latency NoCs design to relax the latency overhead, which include application-specific asynchronous buffer allocation, hardware multicast support, lookahead bypass scheme and short-circuit crossbar channel optimization. / Xin, Ling. / Adviser: Chui-Sing Choy. / Source: Dissertation Abstracts International, Volume: 73-03, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 157-164). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

随着无线通信的蓬勃发展，新的通信标准不断出现，频谱利用率和数据传输速率提高的同时，传输信号的带宽和均峰比也不断增加。此外，多种通信标准共存的现状要求收发机能够在多个载波频率，高效率地传输不同格式的信号。因此，宽带运行和高效的放大高均峰比信号成为了基站功率放大器设计的基本要求。 / Doherty 功率放大器结构简单，增加效率的同时能保持中等线性度，故而受到了广泛关注。本文囊括了三个有关增加Doherty 放大器工作带宽、延展高效率区或提高功率利用因子的创新设计。 / 第一个设计中，复数合路阻抗被用于扩宽Doherty 放大器的高效率区。关于动态阻抗范围，电流比因子和漏极效率的理论分析说明，复数合路阻抗可以当作新的自由度来增加放大器的高效率区。为了验证有关理论，以2GHz 为工作频点，我们使用了相同的基于GaN 工艺的晶体管，分别设计了使用复数合路阻抗和纯实数合路阻抗的Doherty 放大器。连续波测试结果显示，使用复数合路阻抗的Dohety 放大器能够提高9.1dB 的输出回退范围，比基于纯实数合路阻抗的传统设计要高3.6dB。此外，使用单载波、均峰比9.6dB 的WCDMA 信号的测试显示，基于复数合路阻抗的设计在输出功率为33.2dBm 时，其平均漏极效率高达57.4%。 / 第二个设计中使用了随频率变化的复数合路阻抗，通过控制漏极电流，来同时增加Doherty 放大器的工作带宽和高效率区。为了验证有关理论，我们设计了输出功率42dBm、工作带宽1.8-2.2GHz、输出回退区9dB 的Doherty 放大器。连续波测试结果显示，在8.5dB 回退点处，该设计在8.5dB 回退点和饱和输出点的漏极效率分别高达55-59%和69-73%。使用单载波、均峰比9.6dB 的WCDMA 信号的测试显示，该设计在输出功率为33.5dBm 时，其平均漏极效率高达53-58%，邻道抑制比也能保持在-30dBc。 / 最后一个设计中，一种在辅助支路加入变换器的Doherty 结构被用于宽带放大。理论分析显示了该结构能够增加功率利用因子，并提供宽带Doherty 特性。为了验证有关理论，我们设计了输出功率20W、工作带宽1.6-2.4GHz、功率利用因子得到改善的Doherty 放大器。连续波测试结果显示，该设计的功率利用因子高达0.94，所有频点均可得到良好的Doherty 效率特性，该设计在6dB回退点和饱和输出点的漏极效率分别高达55-64%和68-76%。在2GHz 处，使用单载波、均峰比6.6dB 的WCDMA 信号的测试显示，该设计在输出功率为37dBm时，其平均漏极效率高达56%，邻道抑制比低于-37dBc。 / As modern communication system demands higher spectrum efficiency and data rate, new communication standard using complex modulation scheme has emerged and led to transmitting signal with ever-increasing Peak-to-Average Power Ratio (PAPR). Moreover, the co-existence of different standards requires RF transceivers to support signal transmission at multiple carrier frequencies. Therefore, wideband operation and efficient amplification of high PAPR signal are prime requirements for base-station PA design. / For efficiency enhancement, the Doherty Power Amplifier (DPA) [1] has been regarded as the most popular approach due to its circuit simplicity and moderate linearity. Three innovative DPA design techniques relating to the enhancement of operating bandwidth, high efficiency range and power utilization factor (PUF) are proposed in this work. / In the first demonstration, a novel DPA configuration with Complex Combining Load (CCL) is presented to extend the high efficiency range of the amplifier. Theoretical analysis of dynamic load span, current ratio and drain efficiency reveals that complex combining load can offer a new degree of freedom to boost the Output Back-off (OBO) of DPA. For verification, a 2GHz, equal-cell, GaN HEMT-based DPA is simulated, prototyped and measured with both complex and resistive combining loads. Under Continuous Wave (CW) excitation, measurement results show that the CCL DPA can attain an OBO of 9.1 dB which is 3.6 dB higher than that of the RCL design. In addition, by the use of single-carrier WCDMA signal with PAPR of 9.6 dB and at an average output power of 33.2 dBm, the CCL design is found to deliver an average drain efficiency of 57.4%. / The second design presents a novel technique to extend the bandwidth and efficiency range of DPA by the adoption of frequency-varying Complex Combining Load and proper input current control strategy. For verification, a 42 dBm, 1.8-2.2 GHz DPA with OBO of 8.5 dB was designed, built and characterized. Under CW stimulation, a back-off efficiency (8.5 dB) of 55-59% and saturation efficiency of 69-73% were observed over the entire bandwidth. With single carrier WCDMA signal excitation (PAPR of 9.6 dB), an average drain efficiency of 53-58% was obtained at 33.5 dBm average output power and Adjacent Channel Leakage Power Ratio (ACLR) of around -30 dBc. / In the last technique, a novel DPA configuration with auxiliary transformer is presented for broadband operation. Theoretical analysis reveals that the presented design can offer enhanced PUF and wideband Doherty behavior. Based on the proposed theory, a 1.6-2.4 GHz, 20 W DPA with improved PUF is designed, simulated and measured. Under CW excitation, measurement results indicate that the presented DPA can achieve a PUF of 0.94, good Doherty behavior over the entire frequency band with a 6 dB back-off efficiency of 55-64% and saturated efficiency of 68-76%. In addition, by the use of single-carrier WCDMA signal (centered at 2 GHz) with PAPR of 6.6 dB and at an average output power of 37 dBm, an average drain efficiency of 56% is obtained with ACLR of better than -37 dBc. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Fang, Xiaohu. / Thesis (Ph.D.) Chinese University of Hong Kong, 2015. / Includes bibliographical references. / Abstracts also in Chinese.

No description available.

Integrating many processing elements (PE) in a single chip is inevitable as silicon technology allows more than one billion of transistors in a single piece of silicon. Networks-on-Chip (NoCs) has been proposed as a scalable solution to both increasing bandwidth requirements and physical design problems for multi-PE chips. However, as multi-PE chips drive the design focus to shift from the computation-centric to communication-centric, area and power costs consumed by communication has become comparable to what computation consumes. / The second direction is to reduce hop counts of packets when they travel from sources to destinations, and thus to reduce power consumption of NoCs. The reduction of hop counts is realized by using a recently proposed express virtual channel (EVC) technique to virtually bypass intermediate routers. We study the EVC technique in two domains. The first domain is to present a high-level, application-specific methodology to improve power efficiency of EVC paths early in the design stage. The methodology includes three steps. Firstly, aggregate communication loads between routers are calculated. Secondly, an energy reduction model and an energy overhead model are developed. Finally, energy savings of all possible EVCs path are calculated and a greedy algorithm is applied to insert EVCs paths in an iterative way. / The second domain is to exploit the EVC flow control in design and implementation of low-power NoCs. We firstly present cost-efficient hardware components for both EVC source and EVC bypass routers, then propose a statistical approach to customize buffer architectures for EVC networks, then describe creative use of low-power circuit techniques such as clock gating and operand isolation for EVC routers, and finally evaluate EVC NoCs through detailed ASIC implementations. Results show that EVC NoCs can save up to 34.26% of power compared to baseline NoCs. / This thesis tackles design and implementation of cost-efficient NoCs along two orthogonal directions. The first direction is to reduce area and power costs of a single virtual channel router. Through ASIC implementations, we find that allocator logic, including both virtual channel allocator (VA) and switch allocator (SA), consumes a large amount of costs. Based on RTL simulations for the entire NoCs, we identify great opportunities to reduce design costs of VA and then propose two low-complexity allocators: look-ahead VA and combined switch-VC allocator (SVA). Evaluations are performed for a wide range of traffic patterns and router parameters. Results show that both proposed architectures significantly reduce area and power costs of allocators without penalties on network performances. / Zhang, Min. / Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 139-145). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Chung, Wing Kwong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 97-101). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Related Work --- p.3 / Chapter 1.2.1 --- History of Humanoid Robots --- p.3 / Chapter 1.2.2 --- The Study of Humanoid Robots --- p.5 / Chapter 1.3 --- Thesis Overview --- p.6 / Chapter 2 --- Architecture --- p.8 / Chapter 2.1 --- Introduction --- p.8 / Chapter 2.2 --- Mechanical Design --- p.8 / Chapter 2.3 --- Hardware Platform --- p.11 / Chapter 2.4 --- Software Platform --- p.14 / Chapter 3 --- Kinematics --- p.15 / Chapter 3.1 --- Introduction --- p.15 / Chapter 3.2 --- Forward Kinematics --- p.15 / Chapter 3.2.1 --- Lower Limb --- p.17 / Chapter 3.2.2 --- Upper Limb --- p.19 / Chapter 3.3 --- Inverse Kinematics --- p.21 / Chapter 3.3.1 --- Lower Limb --- p.21 / Chapter 3.3.2 --- Upper Limb --- p.24 / Chapter 4 --- Gait Synthesis --- p.29 / Chapter 4.1 --- Introduction --- p.29 / Chapter 4.1.1 --- Difference Between Human and Robot Joints --- p.29 / Chapter 4.1.2 --- Difference Types of Gait for Humanoid Robots --- p.30 / Chapter 4.2 --- Related Works --- p.31 / Chapter 4.3 --- Gait Frame --- p.33 / Chapter 4.3.1 --- Analysis of Human Gait --- p.33 / Chapter 4.3.2 --- Gait Frame for PHR --- p.34 / Chapter 4.4 --- Gait Synthesis --- p.36 / Chapter 4.4.1 --- Mathematic Description of Bezier Curve --- p.36 / Chapter 4.4.2 --- Reasons for Using Bezier Curve for Gait Synthesis --- p.37 / Chapter 4.4.3 --- Gait Synthesis Using Bezier Curve Interpolation --- p.37 / Chapter 4.5 --- Experiments --- p.40 / Chapter 4.5.1 --- Experimental Setup --- p.40 / Chapter 4.5.2 --- Results --- p.40 / Chapter 4.6 --- Discussion --- p.43 / Chapter 4.7 --- Conclusion and Future Work --- p.44 / Chapter 5 --- Balance Algorithm for PHR --- p.45 / Chapter 5.1 --- Introduction --- p.45 / Chapter 5.2 --- Related Works --- p.45 / Chapter 5.3 --- Balance Algorithm --- p.47 / Chapter 5.4 --- Experiments --- p.51 / Chapter 5.4.1 --- Experimental Setup --- p.51 / Chapter 5.4.2 --- Results --- p.51 / Chapter 5.5 --- Discussion --- p.54 / Chapter 5.6 --- Conclusion and Future Work --- p.54 / Chapter 6 --- Human-robot Interaction System through Hand Gestures --- p.55 / Chapter 6.1 --- Introduction --- p.55 / Chapter 6.2 --- Related Works --- p.55 / Chapter 6.3 --- Flow of Hand Gesture Recognition --- p.57 / Chapter 6.4 --- Database Establishment --- p.60 / Chapter 6.4.1 --- Hand Detection and Preprocessing --- p.60 / Chapter 6.4.2 --- Extraction of Features --- p.62 / Chapter 6.4.3 --- Storage of Features --- p.68 / Chapter 6.5 --- Hand Gesture Recognition --- p.69 / Chapter 6.6 --- Experiments --- p.72 / Chapter 6.6.1 --- Experimental Setup --- p.72 / Chapter 6.6.2 --- Recognition Results --- p.73 / Chapter 6.7 --- Discussion --- p.75 / Chapter 6.8 --- Conclusion and Future Work --- p.75 / Chapter 7 --- Conclusion --- p.76 / Chapter 7.1 --- Research Summary --- p.76 / Chapter 7.2 --- Future Work --- p.78 / Chapter A --- Forward Kinematics of PHR --- p.79 / Chapter A.1 --- Lower Limb --- p.79 / Chapter A.2 --- Upper Limb --- p.82 / Chapter B --- Inverse Kinematics of PHR --- p.85 / Chapter B.1 --- Lower Limb --- p.85 / Chapter B.2 --- Upper Limb --- p.88 / Chapter C --- Zero Moment Point --- p.91 / Chapter D --- User Interface of PHR --- p.93