No description available.

No description available.

No description available.

This thesis aims to understand how to design high-performance compression algorithms suitable for hardware implementation and to provide hardware support for an efficient compression algorithm. Lossless data compression techniques have been developed to exploit the available bandwidth of applications in data communications and computer systems by reducing the amount of data they transmit or store. As the amount of data to handle is ever increasing, traditional methods for compressing data become· insufficient. To overcome this problem, more powerful methods have been developed. Among those are the so-called statistical data compression methods that compress data based on their statistics. However, their high complexity and space requirements have prevented their hardware implementation and the full exploitation of their potential benefits. This thesis looks into the feasibility of the hardware implementation of one of these statistical data compression methods by exploring the potential for reorganising and restructuring the method for hardware implementation and investigating ways of achieving efficient and effective designs to achieve an efficient and cost-effective algorithm.

In switched-mode power supplies (SMPS), a Controller is required for output voltage or current regulation. In low-power SMPS, processing power from a fraction of watt to several hundred watts, digital implementations of the controller, i.e. digital controllers have recently emerged as alternatives to the predominately used analog systems. This is mostly due to the better design portability, power management capability, and the potential for implementing advanced control techniques, which are not easy to realize with analog hardware. However, the existing digital implementations are barely functional replicas of analog designs, having comparable dynamic performance if not poorer. Due to stringent constraints on hardware requirements, the digital systems have not been able to demonstrate some of their most attractive features, such as parameter estimation, controller auto-tuning, and nonlinear time-optimal control for improved transient response. This thesis presents two novel digital controllers and systems. The first is an auto-tuning controller that can be implemented with simple hardware and is suitable for IC integration. The controller estimates power stage parameters, such as output capacitance, load resistance, corner frequency and damping factor by examining the amplitude and frequency of intentionally introduced limit cycle oscillations. Accordingly, a digital PID compensator is automatically redesigned and the power stage is adapted to provide good dynamic response and high power processing efficiency. Compared to state of the art analog solutions, the controller has similar bandwidth and improves overall efficiency. To break the control bandwidth limitation associated with the sampling effects of PWM controllers, the second part of the thesis develops a nonlinear dual-mode controller. In steady state, the controller behaves as a conventional PWM controller, and during transients it utilizes a continuous-time digital signal processor (CT-DSP) to achieve time-optimal response. The processor performs a capacitor charge balance based algorithm to achieve voltage recovery through a single on-off sequence of the power switches. Load transient response with minimal achievable voltage deviation and a recovery time approaching physical limitations of a given power stage is obtained experimentally.

In switched-mode power supplies (SMPS), a Controller is required for output voltage or current regulation. In low-power SMPS, processing power from a fraction of watt to several hundred watts, digital implementations of the controller, i.e. digital controllers have recently emerged as alternatives to the predominately used analog systems. This is mostly due to the better design portability, power management capability, and the potential for implementing advanced control techniques, which are not easy to realize with analog hardware. However, the existing digital implementations are barely functional replicas of analog designs, having comparable dynamic performance if not poorer. Due to stringent constraints on hardware requirements, the digital systems have not been able to demonstrate some of their most attractive features, such as parameter estimation, controller auto-tuning, and nonlinear time-optimal control for improved transient response. This thesis presents two novel digital controllers and systems. The first is an auto-tuning controller that can be implemented with simple hardware and is suitable for IC integration. The controller estimates power stage parameters, such as output capacitance, load resistance, corner frequency and damping factor by examining the amplitude and frequency of intentionally introduced limit cycle oscillations. Accordingly, a digital PID compensator is automatically redesigned and the power stage is adapted to provide good dynamic response and high power processing efficiency. Compared to state of the art analog solutions, the controller has similar bandwidth and improves overall efficiency. To break the control bandwidth limitation associated with the sampling effects of PWM controllers, the second part of the thesis develops a nonlinear dual-mode controller. In steady state, the controller behaves as a conventional PWM controller, and during transients it utilizes a continuous-time digital signal processor (CT-DSP) to achieve time-optimal response. The processor performs a capacitor charge balance based algorithm to achieve voltage recovery through a single on-off sequence of the power switches. Load transient response with minimal achievable voltage deviation and a recovery time approaching physical limitations of a given power stage is obtained experimentally.

Thesis (Ph.D. (Computer - Integrated Education)) -- University of Pretoria, 2007. / Includes bibliographical references (leaves 265-284)

Thesis (M.Eng.)--University of Louisville, 2006. / Title and description from thesis home page (viewed Jan. 30, 2007). Department of Computer Engineering and Computer Science. Vita. "July 2006." Includes bibliographical references (p. 61-63).

In general digital control algorithms are multi-input multi-output (MIMO) recursive digital filters, but there are particular numerical requirements in control system processing for which standard processor devices are not well suited, in particular arising in systems with high sample rates. There is therefore a clear need to understand the numerical requirements properly, to identity optimised forms for implementing control laws, and to translate these into efficient processor architectures. By taking a considered view of the numerical and calculation requirements of control algorithms, it is possible to consider special purpose processors that provide well-targeted support of control laws. This thesis describes a compact, high-speed, special-purpose processor which offers a low-cost solution to implementing linear time invariant controllers.

abstract: Mobile electronic devices such as smart phones, netbooks and tablets have seen increasing demand in recent years, and so has the need for efficient, responsive and small power management solutions that are integrated into these devices. Every thing from the battery life to the screen brightness to how warm the device gets depends on the power management solution integrated within the device. Much of the future success of these mobile devices will depend on innovative, reliable and efficient power solutions. Perhaps this is one of the drivers behind the intense research activity seen in the power management field in recent years. The demand for higher accuracy regulation and fast response in switching converters has led to the exploration of digital control techniques as a way to implement more advanced control architectures. In this thesis, a novel digitally controlled step-down (buck) switching converter architecture that makes use of switched capacitors to improve the transient response is presented. Using the proposed architecture, the transient response is improved by a factor of two or more in comparison to the theoretical limits that can be achieved with a basic step down converter control architecture. The architecture presented in this thesis is not limited to digitally controlled topologies but rather can also be used in analog topologies as well. Design and simulation results of a 1.8V, 15W, 1MHz digitally controlled step down converter with a 12mV Analog to Digital Converter (ADC) resolution and a 2ns DPWM (Digital Pulse Width Modulator) resolution are presented. / Dissertation/Thesis / M.S. Electrical Engineering 2013