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Digital control of linear multivariable plants with input and output time delaysChrysanthou, A. January 1985 (has links)
No description available.
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Information, communication and technological competencies in a digital working environment a case study in the Netherlands Defence Organization /Broos, Elizabeth. January 2007 (has links)
Thesis (Ph.D. (Computer - Integrated Education)) -- University of Pretoria, 2007. / Includes bibliographical references (leaves 265-284)
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Evaluation of MILS and reduced kernel security concepts for SCADA remote terminal unitsGuffey, Brent L., January 2006 (has links) (PDF)
Thesis (M.Eng.)--University of Louisville, 2006. / Title and description from thesis home page (viewed Jan. 30, 2007). Department of Computer Engineering and Computer Science. Vita. "July 2006." Includes bibliographical references (p. 61-63).
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Efficient arithmetic using self-timingRamachandran, Ravichandran 02 September 1994 (has links)
The recent advances in VLSI technology have facilitated feature shrinking
and hence a rapid increase in the levels of integration at the chip level. This increase
in the level of integration has brought along with it a host of other constraints, the
most crucial being timing management and increased power dissipation. Such
constraints potentially prevent the full exploitation of the increased processing power
made possible by technological advances.
Timing in complex digital systems has traditionally been managed by using
a global clock, controlled by which all the actions take place in lock-step. An alternative
means of managing timing, called self-timing, simplifies the problems of timing management
and results in a reduced power dissipation of complex digital systems. Systems
designed using this self-timed or asynchronous protocol, work on a principle of handshaking,
running at their own speed, governed by local timers and the availability
of data on which to work. However, this hand-shaking introduces an overhead both
in terms of hardware and computational speed.
The work presented here examines the implementation of an adder, called
a Parallel Half-Adder (PHA), which gains its speed by exploiting the power of asynchrony to calculate the sum. The adder has been implemented in the form of a tunable
micropipeline and compared to traditional adders in terms of hardware complexity
and speed. Comparable results have been obtained, implying that the overhead due
to hand shaking is justified and the performance improvements due to self-timing
can be fully exploited. The design of an array divider using the PHA has also been
presented. / Graduation date: 1995
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Modeling single-event transients in complex digital systems /Clark, Kenneth A. January 2002 (has links) (PDF)
Thesis (Ph. D.)--Naval Postgraduate School, 2002. / Thesis advisor(s): Herschel H. Loomis, Jr., Alan A. Ross. Includes bibliographical references (p. 157-161). Also available online.
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Round off error analysis in digital control systemsAhmed, Moustafa Elshafei. January 1979 (has links)
No description available.
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A DSP based general self-tuning observer controller /Seward, John F. January 1993 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1993. / Typescript. Includes bibliographical references (leaves 64-65).
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Verification of digital controller implementations /Wang, Xuan, January 2005 (has links) (PDF)
Thesis (M.S.)--Brigham Young University. Dept. of Computer Science, 2005. / Includes bibliographical references (p. 55-57).
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Digital control of the hydraulic actuators of an adaptive suspension vehicle /Dworak, Joseph A. (Joseph Alan) January 1985 (has links)
No description available.
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Round off error analysis in digital control systemsAhmed, Moustafa Elshafei January 1979 (has links)
No description available.
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