Better performance has been one of the main motivations behind the recent resurgence of interest in asynchronous circuits (no matter whether this is always true or not). We are particularly interested in the performance of pipelines since they are used extensively in current digital systems. There exists an algorithm that can find the exact upper and lower bounds on the separation time of events in a certain class of process graphs. However, some transformations and complex mathematical analyses, such as graph decomposition for infinite unfolded process graphs must be employed in order to reach exact bounds. This algorithm may be a good candidate for the application of CAD tool development and circuit synthesis, but it tends to block designers from visualizing what factors really affect the performance of asynchronous circuits. In this thesis, a simple approach is adopted to approximate the performance bounds. Since our method is a symbolic approach instead of a numerical approach, it allows designers to analyze the circuit performance while providing design guidelines and approaches at the same time. Our approach has two steps. First, several basic modules are chosen, including FIFO, Fork, Join, Toggle/XOR, Arbiter/Call and Select/XOR. The individual output loop delay, equivalent input delay and equivalent output delay are derived based on the Equal loopdelay theorem. The result is a set of difference equations. The performance approximation can be obtained with simple mathematical operations on the difference equations, given the bounds of stagedelays. That is, the performance bounds of output loop delay, equivalent input delay and equivalent output delay can be represented as the bounds of stagedelays. Second, for a larger system consisting of those basic modules, its performance bounds can be derived directly from the bounds of output loop delay, equivalent input delay and equivalent output delay of those basic modules which have been obtained already. This approach allows a fast and easy calculation of performance bounds, avoiding the need to rederive the difference equations for the whole system. Both modular design and performance approximation are possible with our approach. / Graduation date: 1997

Thesis (Ph. D.)--University of Florida, 2004. / Title from title page of source document. Document formatted into pages; contains 85 pages. Includes vita. Includes bibliographical references.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references (leaves 52-54). Also available in electronic version. Access restricted to campus users.

Yang, Jingling. / "January 2001." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2001. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Chan Wing-kin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 69-72). / Abstracts in English and Chinese. / Abstract of this thesis entitled: --- p.ii / 摘要 --- p.iv / Acknowledgements --- p.v / Table of Contents --- p.vi / List of Figures --- p.viii / List of Tables --- p.x / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview of Communication Systems --- p.1 / Chapter 1.2 --- Soft-output Viterbi Decoder and Turbo Code --- p.2 / Chapter 1.3 --- Iterative Decoding --- p.3 / Chapter 1.4 --- Motivation --- p.3 / Chapter 1.5 --- Organization of the Thesis --- p.4 / Chapter Chapter 2 --- Self-timed Circuit Design Methodology --- p.5 / Chapter 2.1 --- Properties of Self-Timed Design --- p.5 / Chapter 2.2 --- Bundled-data Protocol --- p.7 / Chapter 2.3 --- Two-phase verses Four-phase Handshaking --- p.8 / Chapter 2.4 --- Completion-Detection and Delay Match --- p.9 / Chapter 2.5 --- Muller Pipeline --- p.11 / Chapter 2.6 --- Design of the Adder --- p.12 / Chapter 2.6.1 --- Basic Structure --- p.12 / Chapter 2.6.2 --- Carry Chain and Completion Detection --- p.12 / Chapter Chapter 3 --- SOVA Theory --- p.15 / Chapter 3.1 --- Convolutional Encoder --- p.15 / Chapter 3.2 --- Hard verse Soft Decision Decoding --- p.17 / Chapter 3.3 --- Soft Output Viterbi Algorithm --- p.17 / Chapter 3.3.1 --- Viterbi Algorithm --- p.17 / Chapter 3.3.2 --- Soft Output Algorithm --- p.20 / Chapter Chapter 4 --- Proposed SOVA Decoder Design --- p.24 / Chapter 4.1 --- Overview --- p.24 / Chapter 4.2 --- SOVA Decoder Architecture --- p.24 / Chapter 4.3 --- Branch Metric Unit --- p.26 / Chapter 4.3.1 --- Branch Metric Generation --- p.26 / Chapter 4.3.2 --- Implementation --- p.27 / Chapter 4.4 --- Add-Compare-Select Unit --- p.28 / Chapter 4.4.1 --- Basics --- p.28 / Chapter 4.4.2 --- Self-timed design --- p.28 / Chapter 4.4.3 --- Metric Normalization --- p.30 / Chapter 4.4.4 --- ACS Unit Implementation --- p.31 / Chapter 4.5 --- Traceback Unit --- p.33 / Chapter 4.5.1 --- Viterbi Algorithm Traceback --- p.33 / Chapter 4.5.2 --- Two Step SOVA --- p.34 / Chapter 4.5.3 --- Past Designs --- p.36 / Chapter 4.5.4 --- New Traceback Architecture --- p.38 / Chapter 4.5.5 --- Traceback operation --- p.40 / Chapter 4.5.6 --- Traceback Implementation --- p.42 / Chapter 4.5.7 --- Control Signals --- p.48 / Chapter Chapter 5 --- Experimental Result and Discussion --- p.54 / Chapter 5.1 --- Chip Fabrication --- p.54 / Chapter 5.2 --- Measurements --- p.61 / Chapter Chapter 6 --- Conclusion --- p.67 / References --- p.69 / Appendix --- p.73 / Pin Assignment of the SOVA test chip --- p.73

The counterflow pipeline concept was originated by Sproull et. al.[1] to demonstrate the concept of asynchronous circuits. The basic premise is that a simple architecture with only local communication and control and a simple regular structure will result in increased performance. This thesis attempts to analyze the performance of the basic counterflow pipeline architecture, find the bottlenecks associated with this implementation, and attempt to illustrate the improvements that we have made in overcoming these bottlenecks. From this research, three distinct microarchitectures have been developed, ranging from a synchronous version of the counterflow design suggested by Sproull to an all new structure which supports aggressive speculation, no instruction stalling and ultimately intrinsic multi-threading. To support high-level simulation of various architectures a Java based simulation environment has been developed which was used to explore the various design trade-offs and evaluate the resulting performance of each of the architectures. / Graduation date: 1998

Asynchronous circuits have recently been a breakthrough in many high performance computers. The concept of asynchronous circuits which started a long time ago has slowly grasped the attention of many designers. The Muller-C-element is an important control block in many asynchronous designs and therefore it is important to understand some of the possible failures that might occur in this circuit. The timing and behavior of this element will have an important effect on the overall performance of the system. The purpose of this research is to study some of the common failures that exist in synchronous logic and find out if these failures can also happen in the C-element. Condition for a failure must be present in order for it to occur. Understanding the conditions required for a circuit failure to occur, we will show realistic examples in the applications of C-element in which such similar conditions will also happen. In this thesis, we are interested in analyzing the circuit failures in C-element due to different logic threshold voltages of different devices, problem of charge-sharing and metastabilty characteristic of circuit. Simulations results will show such failures does occur in the C-element when the conditions were met. / Graduation date: 1997

Thesis (M.S.)--University of Texas at Dallas, 2007. / Includes vita. Includes bibliographical references (leaves 149-151)

Thesis (M.S.)--Missouri University of Science and Technology, 2009. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed January 22, 2009) Includes bibliographical references.

The recent advances in VLSI technology have facilitated feature shrinking and hence a rapid increase in the levels of integration at the chip level. This increase in the level of integration has brought along with it a host of other constraints, the most crucial being timing management and increased power dissipation. Such constraints potentially prevent the full exploitation of the increased processing power made possible by technological advances. Timing in complex digital systems has traditionally been managed by using a global clock, controlled by which all the actions take place in lock-step. An alternative means of managing timing, called self-timing, simplifies the problems of timing management and results in a reduced power dissipation of complex digital systems. Systems designed using this self-timed or asynchronous protocol, work on a principle of handshaking, running at their own speed, governed by local timers and the availability of data on which to work. However, this hand-shaking introduces an overhead both in terms of hardware and computational speed. The work presented here examines the implementation of an adder, called a Parallel Half-Adder (PHA), which gains its speed by exploiting the power of asynchrony to calculate the sum. The adder has been implemented in the form of a tunable micropipeline and compared to traditional adders in terms of hardware complexity and speed. Comparable results have been obtained, implying that the overhead due to hand shaking is justified and the performance improvements due to self-timing can be fully exploited. The design of an array divider using the PHA has also been presented. / Graduation date: 1995