Constrained graph problems are about finding graphs respecting a given set of constraints. These problems occur in many areas. For example, security properties, biological reaction mechanisms, ecological predator/prey relationships, compiler code optimizations, and logic circuit fault diagnosis are just a few of the areas in which graph constraints play an important role. This thesis proposes a constraint programming approach for solving these problems. We present new constraints defined on top of the notions of domination and transitive closure, and their search algorithms. We have implemented these constraints in the state-of-the-art Gecode system and shown that they are competitive with or better than other approaches in realistic scenarios. / Les problèmes de graphes contraints concernent la recherche de graphes qui respectent un ensemble donné de contraintes. Ils apparaissent dans de nombreux domaines. Par exemple, la sécurité dans les logiciels, les méchanismes des réactions biologiques, les relations prédateur/proie en écologie, l'optimisation de code par les compilateurs, et le diagnostic de pannes dans des circuits logiques sont quelques-uns des domaines dans lesquels les contraintes de graphes jouent un rôle important. Cette thèse propose une approche basée sur la programmation par contraintes pour résoudre ces problèmes. Nous présentons de nouvelles contraintes définies sur les notions de domination et de clôture transitive, ainsi que leurs algorithmes de recherche. Nous avons implémenté ces contraintes dans le système de pointe Gecode, et avons montré notre approche compétitive et parfois meilleure que d'autres approches dans des cas réalistes.

Constrained graph problems are about finding graphs respecting a given set of constraints. These problems occur in many areas. For example, security properties, biological reaction mechanisms, ecological predator/prey relationships, compiler code optimizations, and logic circuit fault diagnosis are just a few of the areas in which graph constraints play an important role. This thesis proposes a constraint programming approach for solving these problems. We present new constraints defined on top of the notions of domination and transitive closure, and their search algorithms. We have implemented these constraints in the state-of-the-art Gecode system and shown that they are competitive with or better than other approaches in realistic scenarios. / Les problèmes de graphes contraints concernent la recherche de graphes qui respectent un ensemble donné de contraintes. Ils apparaissent dans de nombreux domaines. Par exemple, la sécurité dans les logiciels, les méchanismes des réactions biologiques, les relations prédateur/proie en écologie, l'optimisation de code par les compilateurs, et le diagnostic de pannes dans des circuits logiques sont quelques-uns des domaines dans lesquels les contraintes de graphes jouent un rôle important. Cette thèse propose une approche basée sur la programmation par contraintes pour résoudre ces problèmes. Nous présentons de nouvelles contraintes définies sur les notions de domination et de clôture transitive, ainsi que leurs algorithmes de recherche. Nous avons implémenté ces contraintes dans le système de pointe Gecode, et avons montré notre approche compétitive et parfois meilleure que d'autres approches dans des cas réalistes.

This dissertation is in the area of Computer-Aided Design (CAD) of digital Integrated Circuits (ICs). Today's digital ICs, such as microprocessors, memories, digital signal processors (DSPs), etc., range from a few thousands to billions of logic gates, flip-flops, and other components, packed in a few millimeters of area. The creation of such highly complex systems would not be possible without the use of CAD tools. CAD tools play the key role in determining the area, speed and power consumption of the resulting circuits. We address several problems related to the logic synthesis step of the CAD flow. First, we investigate properties of double-vertex dominators in directed acyclic graphs. We present an O(n) algorithm for identifying all O(n2) double-vertex dominators of a given vertex, where n is the size of the graph. The key to the algorithm's efficiency is a new data structure for representing double-vertex dominators which has O(n) size and can be efficiently manipulated. This work improves the state of the art in double-vertex dominators identification in terms of both space and time complexity. We also show how dominators can be used for structural decomposition of Boolean functions represented by circuit graphs. Next, we present a depth-optimal technology mapping algorithm for look-up table (LUT) based Field Programmable Gate Arrays. This algorithm is two orders of magnitude faster than previous technology mapping algorithms while achieving solution with a smaller number of LUTs. We also consider level-limited decomposition of Boolean functions which is of particular interest for applications which require circuit representations of a limited depth, such as control logic of microprocessors. We present an efficient algorithm for computing the decomposition of type f = g * h + r, where f, g, h and r are Boolean functions. Another contribution of the dissertation is an algorithm for identifying and removing redundancy in combinational circuits. This algorithm provides a quick partial solution which might be more suitable than exact ATPG and SAT-based approaches for redundancy removal runs at the intermediate steps of the CAD flow. It is embedded into the internal logic synthesis tool of IBM. Other contributions of the dissertation are a proof that, for some Reduced Ordered Binary Decision Diagrams, none of the bound-set preserving orderings is best, a proof of the existence of a perfect input assignment which guarantees that two non-equivalent Boolean functions hash to two different values, and a set of efficient algorithms for the analysis of random Boolean networks. / QC 20100914

Today's EDA (Electronic Design Automation) industry faces enormous challenges. Their primary cause is the tremendous increase of the complexity of modern digital designs. Graph algorithms are widely applied to solve various EDA problems. In particular, graph dominators, which provide information about the origin and the end of reconverging paths in a circuit graph, proved to be useful in various CAD (Computer Aided Design) applications such as equivalence checking, ATPG, technology mapping, and power optimization. This thesis provides a study on graph dominators in logic synthesis and verification. The thesis contributes a set of algorithms for computing dominators in circuit graphs. An algorithm is proposed for finding absolute dominators in circuit graphs. The achieved speedup of three orders of magnitude on several designs enables the computation of absolute dominators in large industrial designs in a few seconds. Moreover, the computation of single-vertex dominators in large multiple-output circuit graphs is considerably improved. The proposed algorithm reduces the overall runtime by efficiently recognizing and re-using isomorphic structures in dominator trees rooted at different outputs of the circuit graph. Finally, common multiple-vertex dominators are introduced. The algorithm to compute them is faster and finds more multiple-vertex dominators than previous approaches. The thesis also proposes new dominator-based algorithms in the area of decomposition and combinational equivalence checking. A structural decomposition technique is introduced, which finds all simple-disjoint decompositions of a Boolean function which are reflected in the circuit graph. The experimental results demonstrate that the proposed technique outperforms state-of-the-art functional decomposition techniques. Finally, an approach to check the equivalence of two Boolean functions probabilistically is investigated. The proposed algorithm partitions the equivalence check employing dominators in the circuit graph. The experimental results confirm that, in comparison to traditional BDD-based equivalence checking methods, the memory consumption is considerably reduced by using the proposed technique. / QC 20100804

<p>This work focuses on the usage of dominators in circuit graphs in order to reduce the complexity of synthesis and verification tasks. One of the contributions of this thesis is a new algorithm for computing multiple-vertex dominators in circuit graphs. Previous algorithms, based on single-vertex dominators suffer from their rare appearance in many circuits. The presented approach searches efficiently for multiple-vertex dominators in circuit graphs. It finds dominator relations, where algorithms for computing single-vertex dominators fail. Another contribution of this thesis is the application of dominators for combinational equivalence checking based on the arithmetic transform. Previous algorithms rely on representations providing an explicit or implicit disjoint function cover, which is usually excessive in memory requirements. The new algorithm allows a partitioned evaluation of the arithmetic transform directly on the circuit graph using dominator relations. The results show that the algorithm brings significant improvements in memory consumption for many benchmarks. Proper cuts are used in many areas of VLSI. They provide cut points, where a given problem can be split into two disjoint sub-problems. The algorithm proposed in this thesis efficiently detects proper cuts in a circuit graph and is based on a novel concept of a reduced dominator tree. The runtime of the algorithm is less than 0.4 seconds for the largest benchmark circuit. The final contribution of this thesis is the application of the proper cut algorithm as a structural method to decompose a Boolean function, represented by a circuit graph. In combination with a functional approach, it outperforms previous methods, which rely on functional decomposition only.</p>

This work focuses on the usage of dominators in circuit graphs in order to reduce the complexity of synthesis and verification tasks. One of the contributions of this thesis is a new algorithm for computing multiple-vertex dominators in circuit graphs. Previous algorithms, based on single-vertex dominators suffer from their rare appearance in many circuits. The presented approach searches efficiently for multiple-vertex dominators in circuit graphs. It finds dominator relations, where algorithms for computing single-vertex dominators fail. Another contribution of this thesis is the application of dominators for combinational equivalence checking based on the arithmetic transform. Previous algorithms rely on representations providing an explicit or implicit disjoint function cover, which is usually excessive in memory requirements. The new algorithm allows a partitioned evaluation of the arithmetic transform directly on the circuit graph using dominator relations. The results show that the algorithm brings significant improvements in memory consumption for many benchmarks. Proper cuts are used in many areas of VLSI. They provide cut points, where a given problem can be split into two disjoint sub-problems. The algorithm proposed in this thesis efficiently detects proper cuts in a circuit graph and is based on a novel concept of a reduced dominator tree. The runtime of the algorithm is less than 0.4 seconds for the largest benchmark circuit. The final contribution of this thesis is the application of the proper cut algorithm as a structural method to decompose a Boolean function, represented by a circuit graph. In combination with a functional approach, it outperforms previous methods, which rely on functional decomposition only.