Game designers spend a great deal of time developing balanced game experiences. However, differences in player ability, hardware capacity (e.g. network connections) or real-world elements (as in mixed-reality games), make it difficult to balance games for different players in different conditions. In this research, adaptive time-variant minigames have been introduced as a method of addressing the challenges in time balancing as a part of balancing players of games. These minigames were parameterized to allow both a guaranteed minimum play time (the minimum time to complete a minigames to address the fixed temporal constraints) and dynamic adaptability (the ability of adapting the game during the game play to address temporal variations caused by individual differences). Three time adaptation algorithms have been introduced in this research and the interaction between adaptive algorithm, game mechanic, and game difficulty were analyzed in controlled experiments. The studies showed that there are significant effects and interactions for all three factors, confirming the initial hypothesis that these processes were important and linked to each other. Furthermore, the studies revealed that finer temporal granularity leads to less-perceptible adaptation and smaller deviations in game completion times. The results also provided evidence that adaptation mechanisms allow accurate prediction of play time. The designed minigames were valuable in helping to balance temporal asymmetries in a real mixed-reality game. It was also found that these adaptation algorithms did not interrupt the overall play experience.

The SiC MOSFET has attracted interest due to its superior characteristics compared to its Si counterpart. Several SiC MOSFETs are usually paralleled to increase current capability, considering cost effectiveness and manufacturability. Current unbalance among the MOSFETs is a concern as it affects reliability. The two main causes are asymmetrical layout and parameter mismatch. The variation in parameters, unlike circuit or module layout, is unavoidable during production. Among all the parameters of MOSFET, the spreads in on-state resistance (Rds(on)) and threshold voltage (Vth) are the major concerns during paralleling. The disparity in Rds(on) causes static current unbalance which is self-limited due to the positive temperature coefficient of Rds(on). Its influence is not investigated here. The threshold voltage Vth has a negative temperature coefficient, forcing the MOSFET with lower Vth to carry more current during switching transient. Paralleled MOSFETs are usually de-rated to guarantee safe operation. Balancing of peak currents during switching transient isthe goal of this work. Integration of current/voltage sensors into paralleled structure is difficult in real application. Complicated feedback loop design and separate gate drivers also need to be avoided in perspective of cost and volume. Passive balancing solutions are investigated in this dissertation. The inductors and resistors most effective in improving current sharing are identified by parametric analysis. Their current balancing mechanisms are analyzed in circuit point of view. The design guidelines involving the magnitude of Vth mismatch, current rise time, and unbalance percentage are derived for the selection of passive components. The theory upholds well when substantial parasitics from device package and layout exist. Several passive balancing structures are analyzed and compared in terms of current balancing capability, voltage stress, total switching loss, and switching loss difference. All of them can provide much better current and power balancing without increasing switching loss. Some of the them may increase the stress-inducing inductance, which can be reduced by negative magnetic coupling. Perfect coupling between power-source inductors would enable current matching without penalty on voltage stress. Common-source inductance (Lcm) is effective in dynamic balancing, but at the expense of higher switching loss. It is not considered in power module application because Kelvin connection is normally applied. However, wire bond inside the package of discrete MOSFETs and part of the external leads are inevitable and add to Lcm. Peak-current and switching energy mismatches vary with operating conditions (including input voltage, input current, and switching speed). Design guidelines and procedures that are valid for wide operating range are provided for cases with and without Lcm. This dissertation also models the switching energy and switching energy mismatch of paralleled MOSFETs. The influence of operating conditions, passive balancing components, layout and package parasitic inductances, nonlinear channel performance, and voltage dependent parasitic capacitors are included in the modeling process. The resulting high order system is simplified by reducing the number of passive components and number of devices without losing accuracy. The influence of current balancing components and magnitude of threshold voltage mismatch on sharing are discussed based on modeling results. In conclusion, this dissertation balances the transient currents between paralleled SiC MOSFETs automatically by inductance, resistance and magnetic coupling. This procedure is done utilizing one gate driver without current/voltage sensors and feedback loop. Those solutions work for both polarities of Vth mismatch and force balancing from the first current peak. Design guidelines involving the magnitude of Vth mismatch, current rise time, and maximum peak-current difference are derived to guide the choice of passive components. The detail design procedures are recommended to force currents to share over wide operating range. The aforementioned benefits are demonstrated by two paralleled SiC MOSFETs (C2M0160120D) tested at variant operating conditions. The difference of peak currents can be reduced below 5% of steady-state current in every switching transient. Switching energy mismatch percentage can be reduced by 6 times without increasing total switching energy. / Ph. D. / This research focuses on balancing currents between paralleled SiC MOSFETs. Several SiC MOSFETs are usually paralleled to increase current capability. Current unbalance among MOSFETs caused by variation in parameters is a concern as it affects reliability. Several passive balancing structures are proposed in this dissertation. All of them can provide much better current and power sharing without great scarification of other switching performance. Severity of unbalance varies with operating conditions (including input voltage, input current, and switching speed). Design guidelines and procedures that are valid for a wide operating range are provided. This dissertation also models the switching energy and switching energy mismatch of paralleled MOSFETs. The resulting high order system is simplified by reducing the number of passive components and number of devices without losing accuracy. More findings are discussed based on modeling results. The effectiveness of passive balancing methods are demonstrated by two paralleled SiC MOSFETs tested at variant operating conditions. The difference of peak currents can be reduced below 5% of steady-state current in every switching transient. Switching energy mismatch percentage can be reduced by 6 times without increasing total switching energy.