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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Estimating the Dynamic Sensitive Cross Section of an FPGA Design through Fault injection

Johnson, Darrel E. 15 April 2005 (has links) (PDF)
A fault injection tool has been created to emulate single event upset (SEU) behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the reliability of FPGA designs and fault tolerance schemes to be quickly and accurately tested. The validity of testing performed with this fault injection tool has been confirmed through radiation testing. A radiation test was conducted at Crocker Nuclear Laboratory using a proton accelerator in order to determine the actual dynamic sensitive cross section for specific FPGA designs. The results of this radiation testing were then analyzed and compared with similar fault injection tests, with results suggesting that the fault injection tool behavior is indeed accurate and valid. The fault injection tool can be used to determine the sensitivity of an FPGA design to configuration memory upsets. Additionally, fault mitigation techniques designed to increase the reliability of an FPGA design in spite of upsets within the configuration memory, can be thoroughly tested through fault injection. Fault injection testing should help to increase the feasibility of reconfigurable computing in space. FPGAs are well suited to the computational demands of space based signal processing applications; however, without appropriate mitigation or redundancy techniques, FPGAs are unreliable in a radiation environment. Because the fault injection tool has been shown to reliably model the effects of single event upsets within the configuration memory, it can be used to accurately evaluate the effectiveness of fault tolerance techniques in FPGAs.

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