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The main design requirements for today's mobile applications are: · high throughput performance. · high energy efficiency. · high programmability. Until now, the choice of platform has often been limited to Application-Specific Integrated Circuits (ASICs), due to their best-of-breed performance and power consumption. The economies of scale possible with these high-volume markets have traditionally been able to hide the high Non-Recurring Engineering (NRE) costs required for designing and fabricating new ASICs. However, with the NREs and design time escalating with each generation of mobile applications, this practice may be reaching its limit. Designers today are looking at programmable solutions, so that they can respond more rapidly to changes in the market and spread costs over several generations of mobile applications. However, there have been few feasible alternatives to ASICs: Digital Signals Processors (DSPs) and microprocessors cannot meet the throughput requirements, whereas Field-Programmable Gate Arrays (FPGAs) require too much area and power. Coarse-grained dynamically reconfigurable architectures offer better solutions for high throughput applications, when power and area considerations are taken into account. One promising example is the Reconfigurable Instruction Cell Array (RICA). RICA consists of an array of cells with an interconnect that can be dynamically reconfigured on every cycle. This allows quite complex datapaths to be rendered onto the fabric and executed in a single configuration - making these architectures particularly suitable to stream processing. Furthermore, RICA can be programmed from C, making it a good fit with existing design methodologies. However the RICA architecture has a drawback: poor scalability in terms of area and power. As the core gets bigger, the number of sequential elements in the array must be increased significantly to maintain the ability to achieve high throughputs through pipelining. As a result, a larger clock tree is required to synchronise the increased number of sequential elements. The clock tree therefore takes up a larger percentage of the area and power consumption of the core. This thesis presents a novel Dynamically Reconfigurable Asynchronous Processor (DRAP), aimed at high-throughput mobile applications. DRAP is based on the RICA architecture, but uses asynchronous design techniques - methods of designing digital systems without clocks. The absence of a global clock signal makes DRAP more scalable in terms of power and area overhead than its synchronous counterpart. The DRAP architecture maintains most of the benefits of custom asynchronous design, whilst also providing programmability via conventional high-level languages. Results show that the DRAP processor delivers considerably lower power consumption when compared to a market-leading Very Long Instruction Word (VLIW) processor and a low-power ARM processor. For example, DRAP resulted in a reduction in power consumption of 20 times compared to the ARM7 processor, and 29 times compared to the TIC64x VLIW, when running the same benchmark capped to the same throughput and for the same process technology (0.13μm). When compared to an equivalent RICA design, DRAP was up to 22% larger than RICA but resulted in a power reduction of up to 1.9 times. It was also capable of achieving up to 2.8 times higher throughputs than RICA for the same benchmarks.

Digital image processing and compression technologies have significant market potential, especially the JPEG2000 standard which offers outstanding codestream flexibility and high compression ratio. Strong demand for high performance digital image processing and compression system solutions is forcing designers to seek proper architectures that offer competitive advantages in terms of all performance metrics, such as speed and power. Traditional architectures such as ASIC, FPGA and DSPs have limitations in either low flexibility or high power consumption. On the other hand, through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, coarse-grained dynamically reconfigurable architectures are proving to be strong candidates for future high performance digital image processing and compression systems. This thesis investigates dynamically reconfigurable architectures and especially the newly emerging RICA paradigm. Case studies such as Reed- Solomon decoder and WiMAX OFDM timing synchronisation engine are implemented in order to explore the potential of RICA-based architectures and the possible optimisation approaches such as eliminating conditional branches, reducing memory accesses and constructing kernels. Based on investigations in this thesis, a novel customised dynamically reconfigurable architecture targeting digital image processing and compression applications is devised, which can be tailored to adopt different applications. A demosaicing engine based on the Freeman algorithm is designed and implemented on the proposed architecture as the pre-processing module in a digital imaging system. An efficient data buffer rotating scheme is designed with the aim of reducing memory accesses. Meanwhile an investigation targeting mapping the demosaicing engine onto a dual-core RICA platform is performed. After optimisation, the performance of the proposed engine is carefully evaluated and compared in aspects of throughput and consumed computational resources. When targeting the JPEG2000 standard, the core tasks such as 2-D Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimal Truncation (EBCOT) are implemented and optimised on the proposed architecture. A novel 2-D DWT architecture based on vector operations associated with RICA paradigm is developed, and the complete DWT application is highly optimised for both throughput and area. For the EBCOT implementation, a novel Partial Parallel Architecture (PPA) for the most computationally intensive module in EBCOT, termed Context Modeling (CM), is devised. Based on the algorithm evaluation, an ARM core is integrated into the proposed architecture for performance enhancement. A Ping-Pong memory switching mode with carefully designed communication scheme between RICA based architecture and ARM is proposed. Simulation results demonstrate that the proposed architecture for JPEG2000 offers significant advantage in throughput.

Grammatical Evolution (GE) is a method of utilising a general purpose evolutionary algorithm to ???evolve??? programs written in an arbitrary BNF grammar. This thesis extends GE as follows: GE as an extension of Genetic Programming (GP) A novel method of automatically extracting information from the grammar is introduced. This additional information allows the use of GP style crossover which in turn allows GE to perform identically to a strongly typed GP system as well as a non-typed (or canonical) GP system. Two test problems are presented one which is more easily solved by the GP style crossover and one which favours the tradition GE ???Ripple Crossover???. With this new crossover operator GE can now emulate GP (as well as retaining its own unique features) and can therefore now be seen as an extension of GP. Dynamically Defined Functions An extension to the BNF grammar is presented which allows the use of dynamically defined functions (DDFs). DDFs provide an alternative to the traditional approach of Automatically Defined Functions (ADFs) but have the advantage that the number of functions and their parameters do not need to be specified by the user in advance. In addition DDFs allow the architecture of individuals to change dynamically throughout the course of the run without requiring the introduction of any new form of operator. Experimental results are presented confirming the effectiveness of DDFs. Self-Selecting (or variable) crossover. A self-selecting operator is introduced which allows the system to determine, during the course of the run, which crossover operator to apply; this is tested over several problem domains and (especially where small populations are used) is shown to be effective in aiding the system to overcome local optima. Spatial Co-Evolution in Age Layered Planes (SCALP) A method of combining Hornby???s ALPS metaheuristic and a spatial co-evolution system used by Mitchell is presented; the new SCALP system is tested over three problem domains of increasing difficulty and performs extremely well in each of them.

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Runtime dynamic reconfiguration of field-programmable gate arrays (FPGAs) and devices incorporating microprocessors and FPGA has been successfully utilized to increase performance and reduce power consumption. While previous methods have been successful, they typically do not consider the runtime behavior of the application that can be significantly affected by variations in data inputs, user interactions, and environmental conditions. In this dissertation, we present a dynamically reconfigurable system and design methodology that optimizes performance and power consumption by determining which coprocessors to implement with an FPGA based upon the current application behavior.For dynamically reconfigurable systems, in which the selection of hardware coprocessors to implement within the FPGA is determined at runtime, online estimation methods are essential to evaluate the performance and power consumption impact of the hardware coprocessor selection. We present a base profile assisted online system-level performance and power estimation framework for estimating the speedup and power consumption of dynamically reconfigurable embedded systems.Importantly though, complex interactions between multiple application tasks, non-deterministic execution behavior, and effects of operating system scheduling introduce significant challenges. To address these, we further present an adaptive online performance and power estimation framework suing kernel speedup coefficient adaptation that monitors and adapts the changing application and system behavior for multitasked applications. By exhaustively examining predefined voltage and frequency settings for the microprocessor and hardware kernels, the potential speedup and power reduction can be effectively estimated for each configuration and voltage/frequency settings. These estimates can be utilized to determine the optimal system configuration. At the same time, the kernel speedup coefficients for each kernel can be dynamically updated to account for the difference between the estimated and actual performance measured at runtime.Finally, in order to quickly determine kernel selection and voltage and frequency settlings, we present an efficient, online heuristic performance and power estimation framework that significantly decreases execution time at the cost of a small increase in power consumption. This online heuristic estimation framework achieves significant power reduction compared to software only implementation without performance degradation.

在醫療系統中，存取控管是電子病歷安全防護的核心。針對這樣的議題，我們實驗室已經有設計出一種安全的架構，利用最新的程式開發技術，剖面導向程式設計為基礎，設計出一種宣告式電子病歷安全控管的方法。這樣的設計讓安全管理者可以有系統化的控制整個系統的安全存取。但是這樣的架構下，安全規則的變動必須經過好幾道複雜的手續，造成使用上彈性不足。 本研究針對這樣的架構提出幾種改進的方式，使安全規則更動更具有彈性。主要分為兩方面，第一，針對安全規則的變數，設計可以彈性更動的方式，不需要為了更動變數而重複整個安全控管規則產生流程。第二，利用動態載入的功能，提出可以由外部Java程式寫好安全控管規則，在執行時候將該規則載入來判斷，如此對於複雜的安全控管規則也有修改的彈性。希望藉由這樣彈性的設計使我們設計的安全控管架構更能符合實際使用的需求。 / Maintaining proper access control to Electronic Medical Records (EMR) is essential to protecting patients’ privacy. However, the fine-grained and dynamic nature of access control rules for EMR has imposed great challenges on the healthcare information system developers. This thesis presents a dynamically configurable access control mechanism for Web-based EMR systems.It is an enhancement of a previous work in which static aspects are employed to enforce fine-grained access control for EMR. Specifically, we provide two additional kinds of dynamic adjustment mechanism to enhance the static access control aspects, namely dynamic parameters and dynamic constraints. If the scope of dynamic changes is small, dynamic parameters can realize the required changes. Otherwise, dynamic constraints can be used to support replacement of the access control enforcing code while allowing the EMR application running as usual. Consequently, system administrators have a fine range of choices with different trade-offs between flexibility and performance, namely fully static aspects, parameterized aspects using dynamic parameters and fully dynamic aspects using dynamic constraints. We have built a Web-based EMR prototype implementation using AspectJ to demonstrate our approach.

Walking around in dynamically changing environments require the integration of three of our sensory systems: visual, vestibular, and kinesethic. Vision is the only modality of these three sensory systems that provides information at a distance for proactively controlling locomotion (Gibson, 1958). The visual system provides information about self-motion, about body position and body segments relative to one another and the environment, and environmental information at a distance (Patla, 1998). Gibson (1979) developed the idea that everyday behaviour is controlled by perception-action coupling between an action and some specific information picked up from the optic flow that is generated by that action. Such that visual perception guides the action required to navigate safely through an environment and the action in turn alters perception. The objective of my thesis was to determine how well perception and action are coupled when approaching and walking through moving doors with dynamically changing apertures. My first two studies were grouped together and here I found that as the level of threat increased, the parameters of control changed and not the controlling mechanism. The two dominant action control parameters observed were a change in approach velocity and a change in posture (i. e. shoulder rotation). These findings add to previous work done in this area using a similar set-up in virtual reality, where after much practice participants increased success rate by decreasing velocity prior to crossing the doors. In my third study I found that visual fixation patterns and action parameters were similar when the location of the aperture was predictable and when it was not. Previous work from other researchers has shown that vision and a subsequent action are tightly coupled with a latency of about 1second. I have found that vision only tightly couples action when a specific action is required and the threat of a collision increases. My findings also point in the same direction as previous work that has shown that individuals look where they are going. My last study was designed to determine if we go where we are looking. Here I found that action does follow vision but is only loosely correlated. The most important and common finding from all the studies is that at 2 seconds prior to crossing the moving doors (any type of movement) vision seems to have the most profound effect on action. At this time variability in action is significantly lower than at prior times. I believe that my findings will help to understand how individuals use vision to modify actions in order to avoid colliding with other people or other moving objects within the environment. And this knowledge will help elderly individuals to be better able to cope with walking in cluttered environments and avoid contacting other objects.