Advanced Encryption Standard is new standard for data encryption and decryption.There is a lot of relevant research so far, but how to find out the suitable design according to the demand has become an important question. So we consult different improvement methods from relevant research, do the design space exploration of AES hardware circuit design with the modeling of parameterized IP Generator.We choose non-feedback mode AES design, which can offer higher security. Using the submodule as different design parameter such as SubBytes/InvSubBytes¡BMixColumns/InvMixColumns¡BKeyExpansion to form many kinds of AES hardware circuit. SubBytes/InvSubBytes¡BMixColumns/InvMixColumns module include two different structure, Integrated and Separate Encryption/Decryption module. KeyExpansion module include two different structure, on the fly and Store in Rom.There are three different keylength 128¡B192¡B256, which can form forteen different structure. We provide circuit gate count¡Bthroughput¡Bpower consumption information of different AES hardware citcuit design by the synthesis and gate-level simulation result. According to our implementation, the user can choose the suitable AES hardware circuit design method and which can solve the problem above. We also provide an automatic test pattern generator for our design verification, it makes our design can be integrated efficiently. Our experiment result show that, the design which Encryption/Decryption module use integrated structure have less circuit gate count than which Encryption/Decryption module use separate structure while throughput constraint is between 700MHz to 1300MHz (It¡¦s depend on different keylength combination). But while the throughput constraint become higher, the circuit gate count of integrated structure rise faster than separate structure. And the situation is the same with power consumption.The maximum throughput of KeyExpansion module use store in Rom structure is higher than whcich use on the fly structure.