International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / Improved processing techniques, particularly with respect to parallel computing, are the underlying focus in computer science, engineering, and industry today. Semiconductor technology is fast approaching device physical limitations. Further advances in computing performance in the near future will be realized by improved problem-solving approaches. An important issue in parallel processing is how to effectively utilize parallel computers. It is estimated that many modern supercomputers and parallel processors deliver only ten percent or less of their peak performance potential in a variety of applications. Yet, high performance is precisely why engineers build complex parallel machines. Cumulative performance losses occur due to mismatches between applications, software, and hardware. For instance, a communication system's network bandwidth may not correspond to the central processor speed or to module memory. Similarly, as Internet bandwidth is consumed by modern multimedia applications, network interconnection is becoming a major concern. Bottlenecks in a distributed environment are caused by network interconnections and can be minimized by intelligently assigning processing tasks to processing elements (PEs). Processing speeds are improved when architectures are customized for a given algorithm. Parallel processing techniques have been ineffective in most practical systems. The coupling of algorithms to architectures has generally been problematic and inefficient. Specific architectures have evolved to address the prospective processing improvements promised by parallel processing. Real performance gains will be realized when sequential algorithms are efficiently mapped to parallel architectures. Transforming sequential algorithms to parallel representations utilizing linear dependence vector mapping and subsequently configuring the interconnection network of a systolic array will be discussed in this paper as one possible approach for improved algorithm/architecture symbiosis.

The main objective of our research is to design practical low-density parity-check (LDPC) codes which provide a wide range of code rates in a rate-compatible fashion. To this end, we first propose a rate-compatible puncturing algorithm for LDPC codes at short block lengths (up to several thousand symbols). The proposed algorithm is based on the claim that a punctured LDPC code with a smaller level of recoverability has better performance. The proposed algorithm is verified by comparing performance of intentionally punctured LDPC codes (using the proposed algorithm) with randomly punctured LDPC codes. The intentionally punctured LDPC codes show better bit error rate (BER) performances at practically short block lengths. Even though the proposed puncturing algorithm shows excellent performance, several problems are still remained for our research objective. First, how to design an LDPC code of which structure is well suited for the puncturing algorithm. Second, how to provide a wide range of rates since there is a puncturing limitation with the proposed puncturing algorithm. To attack these problems, we propose a new class of LDPC codes, called efficiently-encodable rate-compatible (E2RC) codes, in which the proposed puncturing algorithm concept is imbedded. The E2RC codes have several strong points. First, the codes can be efficiently encoded. We present low-complexity encoder implementation with shift-register circuits. In addition, we show that a simple erasure decoder can also be used for the linear-time encoding of these codes. Thus, we can share a message-passing decoder for both encoding and decoding in transceiver systems that require an encoder/decoder pair. Second, we show that the non-systematic parts of the parity-check matrix are cycle-free, which ensures good code characteristics. Finally, the E2RC codes having a systematic rate-compatible puncturing structure show better puncturing performance than any other LDPC codes in all ranges of code rates. The throughput performance of incremental redundancy (IR) hybrid automatic repeat request (HARQ) systems highly depends on the performance of high-rate codes. Since the E2RC codes show excellent puncturing performance in all ranges of code rates, especially at high puncturing rate, we verify that E2RC codes outperform in throughput than other LDPC codes in IR-HARQ systems.

This Diploma Thesis analyses an important part of the corporate culture in HILTI Czech Republic, particularly working and private life area balance. It contains improvement suggestions in time management sphere, so the employees work more effective and not only stand the test without detriment to family life and leisure time activities in the hard reality of nowadays, but also being successful.

Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life (from few hours to a few weeks depending on the application). Of late, it was realized that these devices, which are currently being operated at fixed voltage and frequency, are capable of operating at multiple voltages and frequencies. By switching these voltages and frequencies to lower values based upon power requirements, these devices can achieve tremendous benefits in the form of energy savings. Dynamic Voltage and Frequency Scaling (DVFS) techniques have proven to be handy in this situation for an efficient trade-off between energy and timely behavior. Within imec, wearable devices make use of the indigenously developed MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). This system is optimized for efficient and accurate collection, processing, and transfer of data from multiple (health) sensors. MUSEIC v2 has limited means in controlling the voltage and frequency dynamically. In this thesis we explore how traditional DVFS techniques can be applied to the MUSEIC v2. Experiments were conducted to find out the optimum power modes to efficiently operate and also to scale up-down the supply voltage and frequency. Considering the overhead caused when switching voltage and frequency, transition analysis was also done. Real-time and non real-time benchmarks were implemented based on these techniques and their performance results were obtained and analyzed. In this process, several state of the art scheduling algorithms and scaling techniques were reviewed in identifying a suitable technique. Using our proposed scaling technique implementation, we have achieved 86.95% power reduction in average, in contrast to the conventional way of the MUSEIC v2 chip’s processor operating at a fixed voltage and frequency. Techniques that include light sleep and deep sleep mode were also studied and implemented, which tested the system’s capability in accommodating Dynamic Power Management (DPM) techniques that can achieve greater benefits. A novel approach for implementing the deep sleep mechanism was also proposed and found that it can obtain up to 71.54% power savings, when compared to a traditional way of executing deep sleep mode. / Nuförtiden så har multifunktionella bärbara hälsoenheter fått en betydande roll. Dessa enheter drivs vanligtvis av batterier och är därför begränsade av batteritiden (från ett par timmar till ett par veckor beroende på tillämpningen). På senaste tiden har det framkommit att dessa enheter som används vid en fast spänning och frekvens kan användas vid flera spänningar och frekvenser. Genom att byta till lägre spänning och frekvens på grund av effektbehov så kan enheterna få enorma fördelar när det kommer till energibesparing. Dynamisk skalning av spänning och frekvens-tekniker (såkallad Dynamic Voltage and Frequency Scaling, DVFS) har visat sig vara användbara i detta sammanhang för en effektiv avvägning mellan energi och beteende. Hos Imec så använder sig bärbara enheter av den internt utvecklade MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). Systemet är optimerat för effektiv och korrekt insamling, bearbetning och överföring av data från flera (hälso) sensorer. MUSEIC v2 har begränsad möjlighet att styra spänningen och frekvensen dynamiskt. I detta examensarbete undersöker vi hur traditionella DVFS-tekniker kan appliceras på MUSEIC v2. Experiment utfördes för att ta reda på de optimala effektlägena och för att effektivt kunna styra och även skala upp matningsspänningen och frekvensen. Eftersom att ”overhead” skapades vid växling av spänning och frekvens gjordes också en övergångsanalys. Realtidsoch icke-realtidskalkyler genomfördes baserat på dessa tekniker och resultaten sammanställdes och analyserades. I denna process granskades flera toppmoderna schemaläggningsalgoritmer och skalningstekniker för att hitta en lämplig teknik. Genom att använda vår föreslagna skalningsteknikimplementering har vi uppnått 86,95% effektreduktion i jämförelse med det konventionella sättet att MUSEIC v2-chipets processor arbetar med en fast spänning och frekvens. Tekniker som inkluderar lätt sömn och djupt sömnläge studerades och implementerades, vilket testade systemets förmåga att tillgodose DPM-tekniker (Dynamic Power Management) som kan uppnå ännu större fördelar. En ny metod för att genomföra den djupa sömnmekanismen föreslogs också och enligt erhållna resultat så kan den ge upp till 71,54% lägre energiförbrukning jämfört med det traditionella sättet att implementera djupt sömnläge.