This thesis introduces the use of decimal sequences in watermarking to hide information for authentication. The underlying system is based on code division multiple access (CDMA), which is a form of spread spectrum communication. Different algorithms for the use of decimal sequences have been formulated for use in black and white images. The watermark is spread across the carrier image by using the d- sequences of optimal period and retrieval is made by the use of correlation. Matlab version 6.5 was used to implement the algorithms discussed in this thesis. The advantage of using d-sequences over PN sequences is that one can choose from a variety of prime numbers which provides a more flexible system. Different methods for adding the random sequence to the image were investigated and results for random shifts and cyclic shifts have also been discussed.

Opportunities abound in the global content delivery service market and it is here that multicasting is proving to be a powerful feature. In WDM networks, optical splitting is widely used to achieve multicasting. It removes the complications of optical-electronic-optical conversions [1]. Several multicasting algorithms have been proposed in the literature for building light trees. As the amount of fiber deployment increases in networks, the risk of losing large volumes of data traffic due to a fiber span cut or due to node failure also increases. In this thesis we propose heuristic schemes to make the primary multicast trees resilient to network impairments. We consider single link failures only, as they are the most common cause of service disruptions. Thus our heuristics make the primary multicast session survivable against single link failures by offering alternate multicast trees. We propose three algorithms for recovering from the failures with proactive methodologies and two algorithms for recovering from failures by reactive methodologies. We introduce the new and novel concept of critical subtree. Through our new approach the proactive and reactive approaches can be amalgamated together using a criticality threshold to provide recovery to the primary multicast tree. By varying the criticality threshold we can control the amount of protection and reaction that will be used for recovery. The performance of these five algorithms is studied in combinations and in standalone modes. The input multicast trees to all of these recovery heuristics come from a previous work on designing power efficient multicast algorithms for WDM optical networks [1]. Measurement of the power levels at receiving nodes is indeed indicative of the power efficiency of these recovery algorithms. Other parameters that are considered for the evaluation of the algorithms are network usage efficiency, (number of links used by the backup paths) and the computation time for calculating these backup paths. This work is the first to propose metrics for evaluating recovery algorithms for multicasting in WDM optical networks. It is also the first to introduce the concept of hybrid proactive and reactive approach and to propose a simple technique for achieving the proper mix.

We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth.

Device such as remotely located sensors and bio-implanted devices such as gastric pacer require power for operation. The most commonly used energy source for such devices is a battery cell included in the receiver capsule. Wires can also be used with an external power source but in some applications have serious limitations. This work examines a wireless power transmitter and receiver system to provide power to a remotely located microsystem. Inductive power coupling is the method of choice. For gastric pacer application, external transmitter coil can be worn around the waist as a belt and the receiver coil can be a part of a remotely located bio-implanted system. The coupling between transmitter and receiver coils when the diameters are markedly different is analyzed. A conventional rectifier circuit converts ac voltage to required dc voltage. This dc voltage supplies power to the charging chip, which is used to recharge lithium batteries in the implanted system. For an input supply voltage of 0.35 Vrms, the induced voltage in the receiver coil across the load resistor was 0.37 Vrms, when the receiver coil was placed at the center of the transmitter coil. When the receiver coil was placed close to the rim of the transmitter, the induced voltage across the load resistor for the same input supply voltage was 0.67 Vrms. Corresponding transmitted power to the load resistor of the receiver coil were 4 and 13.2 mW, respectively. Means are suggested to improve the power transfer to the receiver coil. The second objective of this thesis is to design an op-amp for on-chip amplification of sensor signals. On-chip detection and amplification are crucial for obtaining high sensitivity and improved signal to noise ratio. Designed op-amp is simulated using PSPICE with Level-3 MOS model parameters. The simulation results show a gain of 40.7 dB and a 3-dB bandwidth of 580 kHz. Experimental measurements made on the fabricated chip observed a gain of 3 and a 3-dB bandwidth of 1 MHz, which was attributed to differences in the values of simulated model parameters and the values appropriate for the fabrication process used by the foundry.

The electric shock absorber is a device that converts the kinetic energy of an oscillating object into electric energy. This kinetic energy is normally dumped in a form of thermal energy in a conventional, mechanical shock absorber. The electric shock absorber consists of a permanent magnet linear synchronous generator (PMLSG), a spring, and an electric energy accumulator. The major goal of the project is to design and analyze the operation of an electric shock absorber. In order to define the initial requirements that the electric shock absorber has to satisfy, the construction and performance of currently used shock absorbers were studied first. With respect to this study, five versions of PMLSG were analyzed qualitatively and the most suitable design was selected. The next subject was the design calculations for the chosen type of PMLSG. To determine the dimensions as well as the parameters of its magnetic and electric circuits, the calculation program was written using MATLAB. The designed PMLSG was studied under steady-state conditions to determine its electromechanical characteristics. For this purpose the mathematical model of the generator was proposed and a program was written in MATLAB that allowed calculating its output parameters under different operation conditions. The PMLSG operates practically in dynamic conditions within the whole system: generator spring controlled rectified battery. The dynamic model of the entire system of the electric shock absorber was proposed and described using the voltage equilibrium equation for the electrical port and the force equilibrium equation for the mechanical port. On the basis of these equations, a block diagram was built and simulations were carried out by using MATLAB-SIMULINK. The performance of the electric shock absorber obtained from simulations was compared with mechanical parameters of the mechanical shock absorber. The conclusion obtained indicates that the electric shock absorber is able to store part of the recovered energy in the battery. However, a great part of this energy is lost in the generator resistance and in the external resistance, which is necessary to be connected to the generator output terminal in order to obtain the desire electromechanical parameters.

Semiconductor feature size continues to decrease permitting superscalar microprocessors to continue to increase the number of functional units available for execution. As the instruction issue width increases beyond the five instruction average basic block size of integer programs, more than one basic block must be issued per cycle to continue to increase instructions per cycle (IPC) performance. Researchers have created methods of fetching instructions beyond the first taken branch to overcome the bottleneck created by the limitations of conventional single branch predictors. We compare the performance of the multiple branch prediction (MBP) and trace cache (TC) fetch unit optimization methods. Multiple branch predictor fetch unit designs issue multiple basic blocks per cycle using a branch address cache and a multiple branch predictor. A trace cache uses the runtime instruction stream to create fixed length instruction traces that encapsulate multiple basic blocks. The comparison is performed by using a SPARC v8 timing based simulator. We simulate both advanced fetch methods and execute benchmarks from the SPEC CPU2000 suite. The results of the simulations are compared and a detailed analysis of both microarchitectures is performed. We find that both fetch unit designs provide a competitive IPC performance. As issue width is increased from an eight to sixteen way superscalar, the IPC performance improves implying that these fetch unit designs are able to take advantage of the wider issue widths. The MBP can use a smaller L1 instruction cache size than the TC and yet achieve a similar IPC performance. Pre-arranged instructions provided by the TC allow the pipeline stages to be shortened in comparison to the MBP. The shorter pipeline significantly improves the IPC performance. Prior trace cache research used two or more ports to the instruction cache to improve the chances of fetching a full basic block per cycle. This was at the expense of instruction cache line realignment complexity. Our results show good performance with a single instruction cache port. We study an approximately equal cost implementation for the MBP and TC. Of the six benchmarks studied, the TC outperforms the MBP over four of the benchmarks.

The problem being tackled here relates to the problem of target tracking in wireless sensor networks. It is a specific problem in localization. Localization primarily refers to the detection of spatial coordinates of a node or an object. Target tracking deals with finding spatial coordinates of a moving object and being able to track its movements. In the tracking scheme illustrated, sensors are deployed in a triangular fashion in a hexagonal mesh such that the hexagon is divided into a number of equilateral triangles. The technique used for detection is the trilateration technique in which intersection of three circles is used to determine the object location. While the object is being tracked by three sensors, distance to it from a fourth sensor is also being calculated simultaneously. The difference is that closest three sensors detect at a frequency of one second while the fourth sensor detects the object location at twice the frequency. Using the distance information from the fourth sensor and a simple mathematical technique, location of object is predicted for every half second as well. The key thing to note is that the forth sensor node is not used for detection but only for estimation of the object at half second intervals and hence does not utilize much power. Using this technique, tracking capability of the system is increased. The scheme proposed can theoretically detect objects moving at speeds of up to 33 m/s unlike the paper [16] on which it is based which can detect objects moving only up to speeds of 5 m/s. While the earlier system [16] has been demonstrated with four sensors as well, but for that the arrangement of sensor nodes is a square. The technique demonstrated does not involve a change in the arrangement and utilizes the hexagonal mesh arrangement. Some other scenarios have been tackled such as when displacement of the object is zero at the end of one second. Its movement is predicted during that time interval. Also, incase an object moves in a circle, such motions are also tracked.

This thesis deals with the mapping of communication of a d-dimensional weak torus on an optical medium. Our results are derived in the setting of a sawtooth slab waveguide. The mapping aims to reduce the number and cost of optical components, by exploiting the fact that not all edges of a weak topology are used simultaneously. This approach allows for a better utilization of the huge bandwidth of an optical slab waveguide; currently the cost and size of optical components external to the optical communication medium are the primary bottleneck of an optical interconnect. We introduce the notion of adjacency and aggregates to model the reusability of optical components across multiple channels. We present methods to map a d-dimensional torus on the optical sawtooth slab waveguide. Specifically, for a One-dimensional torus (or ring), we propose two methods, called mixed aggregate method and the pure aggregate method, that are each nearly optimal. A special case of the pure aggregate method, called separable aggregate mapping, has the added advantage of significantly reducing the optical hardware. For a Two-dimensional torus, we propose a pure aggregate mapping method that has optimal cost where the two dimensions of the torus have relatively prime sizes. We extend this method to a general d-dimensional tori for d > 2. For each of these methods, we also present a scheme that gives the designer the flexibility of using different numbers of modes and wavelengths; the numbers of modes and wavelengths are two primary design parameters for the sawtooth slab waveguide. We also develop lower bounds on the cost of mapping tori on slab waveguides using a separable aggregate mapping. The mapping methods we propose in this thesis have different costs relative to the corresponding lower bounds. Some are optimal and match the lower bound, while for others, there is a gap between the upper and lower bounds. However, all the methods proposed show a marked improvement over a naive mapping. We also explore the possibility of using extra channels to reduce the overall cost in the setting of a hypercube topology.

This work presents an effective built-in current sensor (BICS), which has a very small impact on the performance of the circuit under test (CUT). The proposed BICS works in two-modes the normal mode and the test mode. In the normal mode the BICS is isolated from the CUT due to which there is no performance degradation of the CUT. In the testing mode, our BICS detects the abnormal current caused by permanent manufacturing defects. Further more our BICS can also distinguish the type of defect induced (Gate-source short, source-drain short and drain-gate short). Our BICS requires neither an external voltage source nor current source. Hence the BICS requires less area and is more efficient than the conventional current sensors. The circuit under test is a 10-bit digital to analog converter using charge-scaling architecture.

This thesis deals with the optimization of program size and performance in current generation embedded digital signal processors (DSPs) by the design of optimal memory layouts for data. Given the tight constraints on the size, power consumption, cost and performance of these processors, the minimization of code size in terms of the number of instructions required and the associated reduction in execution time are important. Several DSPs provide limited addressing modes and the layout of data, known as offset assignment, plays a critical role in determining the code size and performance. Even the simplest variant of the offset assignment problem is NP-complete. Research effort in this area has focused on the design, implementation and evaluation of effective heuristics for several variants of the offset assignment problem. One of the most important factors in the determination of the size, and hence, execution time of a code is the number of instructions required to access the variables stored in the processor memory. The indirect addressing mode common in DSPs requires memory accesses to be realized through address registers that hold the address of the memory location to be accessed. The architecture provides instructions for adding to and subtracting from the values of the address registers to compute the addresses of subsequent data that need to be accessed. In addition, some DSP processors include multiple memory banks that allow increased parallelism in memory access. Proper partitioning of variables across memory banks is critical to effectively using the increased parallelism. The work reported in this thesis aims to evolve efficient methods for designing memory layouts under the conditions of availability of one address register (SOA) or of multiple address registers (GOA). It also proposes a novel technique for choosing the assignment of variables to the memory banks. This thesis motivates, proposes and evaluates heuristics for all these three problems. For the SOA and GOA problems, the heuristics are implemented and tested on different random sample inputs, and the results obtained are compared to those obtained by prior heuristics. In addition, this thesis provides some insight into the SOA, GOA and the variable partitioning problems.