<p> Wireless sensor networks experience an increase of attacks in networks in term of security. However, broadcast communication is an essential algorithm that provides a great benefit for large scale communications, especially in Building Automation System (BAS). Embedding the security in this area becomes the top priority for every industry. TESLA protocol is an algorithm that verifies and authenticates senders and has low overhead and a robust authentication mechanism. The appeal of TESLA motivates us to apply this protocol into a hierarchical wireless network architecture for BAS that has a high flexibility for formation networks. To combine these two architectures we implement the knowledge of zero knowledge protocol and a session key cryptography into the formation phase, and modify packets that were used in this phase to make TESLA-alpha protocol compatible with BAS.</p>

<p> Quantum-dot Cellular Automata (QCA) are proposed models of quantum computation, which are articulated in analogy to Von Neumann's conventional models of cellular automata. These models are worthy for the architecture of ultra-dense low-power and high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. Since the design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This project demonstrates a new design approach oriented to the implementation of binary comparators using QCA. This strategy is implemented for designing various architectures of binary comparator. With respect to existing counterparts, the comparators proposed here exhibit significantly higher speed and reduced overall area.</p>

<p> The complexity of the manufacturing process has motivated manufacturers to consider testability as a requirement to assure the reliability and the functionality of each of their designed circuits. One of the most well-known test techniques is called Built-In-Self-Test (BIST). A BIST Universal Asynchronous Receive/Transmit (UART) has the objectives to firstly satisfy specified testability requirements and to secondly generate the lowest-cost with the highest performance implementation. UART has been an important input/output tool for decades and is still widely used. Although BIST techniques are becoming more common in industry, the additional BIST circuit that increases the hardware overhead increases design time and performance degradation is often cited as the reason for the limited use of BIST. </p><p> This project focuses on the design of a UART chip with embedded BIST architecture using Field Programmable Gate Array (FPGA) technology. The paper describes the problems of Very-Large-Scale-Integrated (VLSI) testing followed by the behavior of UART circuit using Verilog. In the implementation phase, the BIST technique will be incorporated into the UART design before the overall design is synthesized by means of reconfiguring the existing design to match testability requirements. The UART is targeted at broadband modems, base stations, cell phones and other designs. BIST is a design technique that allows a circuit to test itself. In this project, the test performance achieved with the implementation of BIST is proven to be adequate to offset the disincentive of the hardware overhead produced by the additional BIST circuit. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production.</p>

<p> Signal classification or automatic modulation classification is an area of research that has been studied for many years, originally motivated by military applications and in current years motivated by the development of cognitive radios. Its functions may include the surveillance of signals of interest and providing information to blind demodulation systems.</p><p> The problem of classifying Code Division Multiple Access (CDMA) signals in the presence of Additive White Gaussian Noise (AGWN) is explored using Decision Theory. Prior state-of-the-art has been limited to single channel digital signals such as MPSK and QAM, with few limited attempts to develop a CDMA classifiers. Such classifiers make use of the cyclic correlation spectrum for single user and feature-based neural network approach for multiple user CDMA. Other approaches have focused on blind detection, which could be used for classification in an indirect manner.</p><p> The discussion is focused on the development of classifiers using the average likelihood function. This approach will ensure that the development is optimal in the sense of minimizing the error in classification when compared with any other types of classification techniques. However, this approach has a challenging problem: it requires averaging over many unknown parameters and can become an intractable problem.</p><p> This research was successful in reducing some of the complexity of this problem. Starting with the definition of the probability of the code matrix and the development of the likelihood of MPSK signals, it was possible to find an analytical solution for CDMA signals with a small code length. Averaging over matrices with the lowest Total Squared Correlation (TSC) allowed simplifying the equations for higher code lengths. The resulting algorithm was tested using Receiver Operating Characteristic Curves and Accuracy versus Signal-to-Noise Ratio (SNR). The algorithm that classifies CDMA in terms of code length and number of active users was extended to different complex types of CDMA under the assumptions of full-loaded, underloaded, balanced and unbalanced CDMA, for orthogonal or quasi-orthogonal codes, and chip-level synchronization. </p>

<p> The problem of data gathering is considered in a wireless sensor network using mobile elements. In particular, we consider a case where data is produced at a particular node and it needs to be delivered to a predefined sink in a given time interval. Mobile elements in a wireless sensor network travel in a predefined path; they collect the data from the nodes and they deliver it to the sink. Each and every node must be visited by the mobile element, which must reach the sink within a given time constraint. Therefore, the goal is to plan a path for the mobile element that minimizes the total length travelled. We propose an algorithmic solution that builds node-disjoint tours that always include the sink, that cover the network and also optimize the total length travelled. We provide an Integer Linear Programming Algorithm (LPF) for the problem and propose two heuristic approaches for building the tours. We also evaluate the performance of our algorithm by comparing it to our optimal solution, also working on few alternative heuristic, commonly used in time-window vehicle routing problems, and demonstrating the superiority of our solution.</p>

<p> In this thesis, we describe a different implementation for in loop filtering method for 3D-HEVC. First we propose the use of adaptive loop filtering (ALF) technique for 3D-HEVC standard in-loop filtering. This filter uses Wiener-based method to minimize the Mean Squared Error between filtered pixel and original pixels. The performance of adaptive loop filter in picture based level is evaluated. Results show up to of 0.2 dB PSNR improvement in Luminance component for the texture and 2.1 dB for the depth. In addition, we obtain up to 0.1 dB improvement in Chrominance component for the texture view after applying this filter in picture based filtering. Moreover, a design of an in-loop filtering with Fast Bilateral Filter for 3D-HEVC standard is proposed. Bilateral filter is a filter that smoothes an image while preserving strong edges and it can remove the artifacts in an image. Performance of the bilateral filter in picture based level for 3D-HEVC is evaluated. Test model HTM- 6.2 is used to demonstrate the results. Results show up to of 20 percent of reduction in processing time of 3D-HEVC with less than affecting PSNR of the encoded 3D video using Fast Bilateral Filter.</p>

<p> Digital Signal Processing (DSP) processors are used in personal computers, smart phones, multimedia devices, etc. Traditional DSP processors with custom logic must meet the demand for increased processing speed. The main aim of the project is to design a 32-bit integer arithmetic processor and to implement it. This design has three major processing features. First, the speed must be optimized by using a hazard free control unit. Second, it must have a two stage pipeline. Third, a single cycle multiply accumulator is utilized. The main advantage of the two stage pipeline is that it can manipulate the instructions, and it can produce correct cycle timing even though there may be hazards. A reduced instruction set is used in this design. A filtering operation is included in order to differentiate the DSP processor from a traditional processor. The processor is designed using Harvard architecture in which both data memory and program memory are accessed simultaneously. This design increases the processing speed by 30%.</p>

<p> Cognitive radios are the external sensing agents for the secondary users to improve the Dynamic Spectrum Access (DSA), to overcome the primary user&rsquo;s problems, and to improve the spectrum utilization. External sensors create the opportunities for the DSA networks to utilize spectrum access within the cellular frequency bands. In this project, a method based on co-operative matching is presented, to overcome the difficulties of managing the detected spectrum by the external sensors. </p><p> The spectrum access resources detected are divided into two types of blocks: massive block size and small block size. In massive block size, secondary users follow wholesale sharing and in the small block size, users follow aggregation sharing. Distributed Fast Spectrum Sharing (DFSS) algorithms reduce the delay in spectrum sharing. Simulation results show that the DSA networks can access 95% of the detected spectrum using a DFSS algorithm. </p>

<p> This project presents a method for detecting node failure in a wireless sensor network. The defective node is identified using round-trip delay measurements. Data transfer from the transmitter section to the receiver section is accomplished via the ZigBee protocol. As soon as a node has been identified as defective, the node is removed from the sensor network. Information about the failed node is provided to users with registered mobile device through the Global System for Mobile (GSM) module. The proposed method has been successfully implemented and tested experimentally on a small sensor network using the LPC2148 ARM7 microcontroller.</p>

<p> This report describes two enhancements implemented on an existing anthropomorphic robot with eight degrees of freedom. The robot is controlled with natural human body motion, i.e., it mimics the body movement, using a Microsoft&reg; Kinect&trade; sensor. The robot&rsquo;s arms are modeled after a three-link manipulator and are controlled through the application of inverse kinematics and geometry generated by the Microsoft&reg; Kinect&trade; sensor data. The two enhancements are wireless control via Bluetooth connection and improvement on the robot movements by applying a Kalman filter to the control system. </p>