While extremely scaled CMOS transistors are believed to cause many design concerns especially for conventional analog circuits, CMOS technology scaling, on the other hand, has also opened up new opportunities for analog and mixed-mode circuit designs to mitigate design challenges by the speed improvement and the high density of the nanometer devices. Phase-locked-loop-based frequency synthesizers are essential building blocks in almost all the communication systems. The design of PLLs is a true mixed signal design challenge covering from high speed analog and RF blocks (VCO), to high speed digital blocks (dividers), to low speed analog (charge pump and loop filter) and low speed digital (phase frequency detector) circuits. In this thesis, we study design challenges and present corresponding solutions to realize PLLs in the nano-scale CMOS era. In particular we focus on supply voltage scaling, area scaling, ultra-wide frequency range, and ultra-low noise performance. An ultra low voltage (ULV) 2.5-GHz GFSK modulator implemented in a 90-nm CMOS technology using only standard digital regular Vt (RVT) devices will first be introduced to address robustness concerns and speed issues due to the supply voltage scaling (down to 0.5V). Then, a 2.5-GHz ultra-compact (150um x 280um) analog PLL implemented in a 45-nm CMOS technology with a fully integrated LC-VCO and an on-chip passive R-C loop filter will further be used to show that area scaling can indeed be achieved for a PLL through a rigorous area-scaling scheme of LC oscillators and a new loop filter structure. New emerging applications such as software-defined radios or highly integrated test instrumentation require the PLL synthesizer to have ultra wide bandwidth and ultra low phase noise. We will present the approaches to mitigate these challenging design objectives by exploiting the capabilities of nanometer transistors. A wideband synthesizer covering from 125MHz to 32GHz with a constant performance across the entire frequency range will be presented; the scaling schemes and design methodologies to achieve constant noise performance across the ultra-wide frequency range will be discussed. Finally, an ultra low noise fractional-N synthesizer will be presented to show how low phase noise fractional-N frequency synthesis can be achieved by taking the full advantage of nano-scale CMOS transistors.

Growing demands on future data centers and high-performance computing systems are driving the development of processor-memory interconnects with greater performance and flexibility than can be provided by existing electronic interconnects. A redesign of the systems' memory devices and architectures will be essential to enabling high-bandwidth, low-latency, resilient, energy-efficient memory systems that can meet the challenges of exascale systems and beyond. By leveraging an optics-based approach, this thesis presents the design and implementation of an optically-connected memory system that exploits both the bandwidth density and distance-independent energy dissipation of photonic transceivers, in combination with the flexibility and scalability offered by optical networks. By replacing the electronic memory bus with an optical interconnection network, novel memory architectures can be created that are otherwise infeasible. With remote optically-connected memory nodes accessible to processors as if they are local, programming models can be designed to utilize and efficiently share greater amounts of data. Processors that would otherwise be idle, being starved for data while waiting for scarce memory resources, can instead operate at high utilizations, leading to drastic improvements in the overall system performance. This work presents a prototype optically-connected memory module and a custom processor-based optical-network-aware memory controller that communicate transparently and all-optically across an optical interconnection network. The memory modules and controller are optimized to facilitate memory accesses across the optical network using a packet-switched, circuit-switched, or hybrid packet-and-circuit-switched approach. The novel memory controller is experimentally demonstrated to be compatible with existing processor-memory access protocols, with the memory controller acting as the optics-computing interface to render the optical network transparent. Additionally, the flexibility of the optical network enables additional performance benefits including increased memory bandwidth through optical multicasting. This optically-connected architecture can further enable more resilient memory system realizations by expanding on current error dectection and correction memory protocols. The integration of optics with memory technology constitutes a critical step for both optics and computing. The scalability challenges facing main memory systems today, especially concerning bandwidth and power consumption, complement well with the strengths of optical communications-based systems. Additionally, ongoing efforts focused on developing low-cost optical components and subsystems that are suitable for computing environments may benefit from the high-volume memory market. This work therefore takes the first step in merging the areas of optics and memory, developing the necessary architectures and protocols to interface the two technologies, and demonstrating potential benefits while identifying areas for future work. Future computing systems will undoubtedly benefit from this work through the deployment of high-performance, flexible, energy-efficient optically-connected memory architectures.

The push for higher levels of performance drives research and innovation in all areas of electronics. Thus far, shrinking circuit sizes and development of new material systems have satisfied this need. Continued scaling and material improvements have become increasingly difficult; simultaneously, more functionality is needed in smaller spaces. Advanced integration techniques provide a solution by engineering together previously incompatible systems. The fabrication of high-performance devices typically requires high temperature processing steps. Since fabrication occurs sequentially, the high temperature prevents the direct integration of two high-performance layers, as completed devices cannot withstand the processing temperatures of subsequent steps. There are significant challenges to integrating process-incompatible systems, and techniques such as wafer bonding, heteroepitaxial growth, and various thin film technologies have shown limited success. In this work, advanced integration is achieved through laser crystallization processes. Unique to laser methods is the ability to locally heat the surface of a material while keeping the underlying substrate at room temperature. This property allows for high performance electronic materials to be integrated with substrates of different functionalities. This thesis focuses on three key components for advanced integration: 1. Laser-crystallized electronic devices, 2. Relevant substrates for integration, and 3. The feasibility of integrating of laser-crystallized devices with low-temperature substrates. Two types of laser-crystallized devices are explored. Thin-film, laser-crystallized silicon transistors are fabricated at low-temperatures and exhibit high mobilities above 400 cm2 2/Vs. Vertical structure diodes built from laser-crystallized silicon outperformed epitaxially-grown diodes of the same geometry. Light emitting diode (LED) arrays are fabricated from compound semiconductor substrates and tested for display applications. These LED arrays are envisioned to sit underneath the laser-crystallized devices, enabling new applications where both high brightness and high performance transistors are needed. Substrates of low-κ dielectric material are also of interest, as they are widely used for their low capacitance properties. Preliminary results suggest that laser crystallization of silicon can be successfully performed on a low-κ dielectric. In addition to enabling new device architectures, it is important for laser crystallization methods to leave the underlying layers unaffected. Simulations of the laser irradiation process predict substrate temperatures to reach only 70C even when the surface reaches the melting temperature of silicon (1400C). Integration feasibility is further investigated with measurements on conventional front-end field effect transistors. When comparing properties from wafers with and without laser processing, no changes in transistor characteristics are observed. In all three components of work, proof-of-principle devices and concepts lay out the groundwork for future investigation. The developed technologies have promising applications in both the microelectronics and display industry. In particular, the integration of LEDs and laser-crystallized silicon enables a high-brightness microdisplay platform for head-mounted displays, pico projectors, and head-up displays.

In the power-starved wireless sensor node application, the main transceiver has to be duty-cycled to prolong the node battery lifetime. Wake-up is among the lowest power schemes to accomplish this; an always ON low-power receiver called the wake-up receiver is used to turn ON the main receiver when needed. In this thesis, we have demonstrated ultra-low-power wake-up by using through-air wireless ultrasound. We have achieved more than an order of magnitude reduction in wake-up receiver power consumption, compared to conventionally used radio frequencies. An ultra-low-power ultrasonic wake-up receiver IC was designed in a 65-nm CMOS process and has a power consumption of only 4.4 uW. For the proof-of-concept prototype demonstrated in this work, the digital back-end circuits were been implemented on a commercial FPGA. An ultrasound data network consisting of three receivers and one transmitter was set up in a lecture hall. For a transmit power of 27 uW, less than 10 % of the wake-up packets, at 1 pkt/s, were missed at each of the three receivers. All the system blocks: receiver IC, ultrasound communication channel and TX-RX transducer pair, were individually characterized in different environments to understand the interaction between the electrical and mechanical domains. Also presented are techniques for increasing the distance ranges of wireless ultrasound and communication schemes for extending the use of ultrasound to environments where line-of-sight communication is not possible.

Integration of alternative materials and devices with CMOS will expand functionality and improve performance of established applications in the era of diminishing returns from Moore's Law scaling. In particular, integration of thin-film magnetic materials will enable improvements in energy efficiency of digital computing applications by enabling integrated power conversion and management with on-chip power inductors. Integrated voltage reg- ulators will also enable fine-grained power management, by providing dynamic scaling of the supply voltage in concert with the clock frequency of synchronous logic to throttle power consumption at periods of low computational demand. Implementation of integrated power conversion requires high capacity energy storage devices. This is best achieved with integration of thin-film magnetic materials for high quality on-chip power inductors. This thesis describes a body of work conducted to develop integrated switch-mode voltage regulators with thin-film magnetic power inductors. Soft-magnetic materials and inductor topologies are selected and optimized, with intent to maximize efficiency and current density of the integrated regulators. Custom integrated circuits are designed and fabricated in 45nm-SOI to provide the control system and power-train necessary to drive the power inductors. A silicon interposer is designed and fabricated in collaboration with IBM Research to integrate custom power inductors by 2.5D chip stacking, enabling power conversion with current density greater than 10A/mm2. The concepts and designs developed from this work will enable significant improvements in performance-per-watt of future microprocessors.

The design of the next-generation Internet infrastructure is driven by the need to sustain the massive growth in bandwidth demands. Novel, energy-efficient, optical networking technologies and architectures are required to effectively meet the stringent performance requirements with low cost and ultrahigh energy efficiencies. In this thesis, a cross-layer communications platform is proposed to enable greater intelligence and functionality on the physical layer. Providing the optical layer with advanced networking capabilities will facilitate the dynamic management and optimization of optical switching based on performance monitoring measurements and higher-layer attributes. The cross-layer platform aims to create a new framework for networks to incorporate packet-scale measurement subsystems and techniques for monitoring the health of the optical channel. This will allow for quality-of-service- and energy-aware routing schemes, as well as an enhanced awareness of the optical data signals. This thesis first presents the design and development of an optical packet switching fabric. Leveraging a networking test-bed environment to validate networking hypotheses, advanced switching functionalities are demonstrated, including the support for quality-of-service based routing and packet multicasting. The investigated cross-layering is based on emerging optical technologies, enabling packet protection techniques and packet-rate switching fabric reconfiguration. Coupled with fast performance monitoring, the platform will achieve significant performance gains within the endeavor of all-optical switching. Allowing for a more intelligent, programmable optical layer aims to support greater flexibility with respect to bandwidth allocation and potentially a significant reduction in the network's energy consumption. The ultimate deliverable of this work is a high-performance, cross-layer enabled optical network node. The experimental demonstration of an initial prototype creates a dynamic network element with distributed control plane management, featuring fast packet-rate optical switching capabilities and embedded physical-layer performance monitoring modules. The cross-layer box enables an intelligent traffic delivery system that can dynamically manipulate optical switching on a packet-granular scale. With the goal of achieving advanced multi-layer routing and control algorithms, the network node requires an intelligent co-optimization across all the layers. The proposed cross-layer design should drive optical technologies and architectures in an innovative way, in order to fulfill the void between the design of basic photonic devices and the networking protocols that use them. The performance of the entire network -- from the optical components, to the routing algorithms and user applications -- should be optimized in concert. This contribution to the area of cross-layer network design creates an adaptable optical pipe that is extremely flexible and intelligent aware of both the physical optical signals and higher-layer requirements. The impact of this work will be seen in the realization of dynamic, energy-efficient optical communication links in future networking infrastructures.

It is an ongoing effort to improve field-effect transistor (FET) performance. With silicon transistors approaching their physical limitations, alternative materials that can outperform silicon are required. Graphene, has been suggested as such an alternative mainly due to its two-dimensional (2D) structure and high carrier velocities. The band structure limits achievable bandgaps, preventing digital electronic applications. This, however, does not rule out analog electronic applications at high frequencies, where the full potential of improved carrier speeds in graphene can be exploited. In this thesis, the high-bias characteristics of graphene FETs are investigated. Current saturation as well as the effect of ambipolar conduction on the current-voltage characteristics are studied. A field-effect model is developed that can capture the effects of the unique band structure, such as a density-dependent saturation velocity. The effect of channel length scaling in these devices is studied down to 100-nm channel length with the aid of pulsed-measurement techniques. Transistors RF performance and bias dependence of high frequency behavior is explored. Novel fabrications methods are developed to improve FET performance. A technique is developed to grow metal-oxides on graphene surface for efficient gate coupling. An alternative approach to making high quality devices is realized by incorporating hexagonal-boron nitride as a gate dielectric. These transistors exhibit the potential of graphene electronics for high-performance analog electronic applications.

Energy Harvesting Active Networked Tags (EnHANTs) are a new type of wireless device in the domain between RFIDs and sensor networks. Future EnHANTs will be small, flexible, and self-powered devices that can be attached to everyday objects that are traditionally not networked to enable "Internet of Things" applications. This work describes the design and development of the EnHANT prototypes and testbed. The current prototypes use thin-film photovoltaics optimized for indoor light harvesting, form multihop networks using ultra-low-power Ultra-Wideband Impulse Radio (UWB-IR) transceivers, and implement energy harvesting adaptive networking protocols. The current testbed enables the evaluation of different algorithms by exposing individual prototypes to repeatable light conditions based on real-world irradiance data. New approaches to characterizing the energy available to energy harvesting devices were explored. A mobile data-logger was used to record the intensity of ambient light, determine the light source, and record the acceleration from motion during different real world activities. These traces were used to model the behavior of photovoltaic and inertial energy harvesters in real world deployments and can be replayed in the EnHANTs testbed. In addition, new techniques to evaluate the efficiency of different photovoltaic technologies under indoor illumination were developed. A proof-of-concept system was built to characterize photovoltaics under a standardized set of conditions in which the radiant intensity and spectral composition of the light source were systematically varied. Techniques to structure student research projects within the EnHANTs project were developed. Project-based learning approaches were implemented to engage students using real-world system development constraints. A survey of the students showed that this approach is an effective method for developing technical, professional, and soft skills. Open source hardware was also applied to EnHANTs project and extended into other domains. A laboratory-based class in flat panel display technology was developed. The course introduces fundamental concepts of display systems and reinforces these concepts through the fabrication of three display devices. A lab kit platform was developed to enable remote students to use low-cost, course specific hardware to complete the lab exercises remotely. This platform was also applied to external projects targeted at non-university students. A workshop was developed to teach artists, designers, and hobbyists how to design and build custom user interfaces using thin-film electronics and rapid prototyping tools. Surveys of the students and workshop participants showed that this platform is an effective teaching tool and can be easily adapted and expanded.

Merging chemical and biomolecular sensors with silicon integrated circuits has the potential to push complex electronics into a low-cost, portable platform, greatly simplifying system- level instrumentation and extending the reach and functionality of point of use technologies. One such class of sensor, the thin-film bulk acoustic resonator (FBAR), has a micron-scale size and low gigahertz frequency range that is ideally matched with modern complementary metal-oxide-semiconductor (CMOS) technologies. An FBAR sensor can enable label-free detection of analytes in real time, and CMOS integration can overcome the measurement complexity and equipment cost normally required for detection with acoustic resonators. This thesis describes a body of work conducted to integrate an array of FBAR sensors with an active CMOS substrate. A monolithic fabrication method is developed, which allows for FBAR devices to be built directly on the top surface of the CMOS chip through post-processing. A custom substrate is designed and fabricated in 0.18 µm CMOS to support oscillation and frequency measurement for each sensor site in a 6×4 array. The fabrication of 0.8-1.5 GHz FBAR devices is validated for both off-chip and on-chip devices, and the integrated system is characterized for sensitivity and limit of detection. On-chip, parallel measurement of multiple sensors in real time is demonstrated for a quantitative vapor sensing application, and the limit of detection is below 50 ppm. This sensor platform could be used for a broad scope of label-free detection applications in chemistry, biology, and medicine, and it demonstrates potential for enabling a low-cost, point of use instrument.

This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit.