The RF circuitry in the physical layer of any wireless communication node is arguably its most important part. The front-end radio is the hardware that enables communication by transmitting and receiving information. Without a robust and high performance front-end, all other higher layers of signal processing and data handling in a wireless network are irrelevant. This thesis investigates the radio circuitry of wireless-networked nodes, and introduces several proposals for improvement. As an emerging market, analysis starts by examining available and ratified network standards suitable for low power applications. After identifying the IEEE 802.15.4 standard (commercially known as ZigBee) as the one of choice, and analysing several front-end architectures on which its transceiver circuitry can be based, an application, the Tyre Pressure Monitoring System (TPMS) is selected to examine the capabilities of the standard and its most suitable architecture in satisfying the application’s requirements. From this compatibility analysis, the most significant shortcomings are identified as interference and power consumption. The work presented in this thesis focuses on the power consumption issues. A comparison of available high frequency transistor technologies concludes Silicon CMOS to be the most appropriate solution for the implementation of low cost and low power ZigBee transceivers. Since the output power requirement of ZigBee is relatively modest, it is possible to consider the design of a single amplifier block which can act as both a Low Noise Amplifier (LNA) in the receiver chain and a Power Amplifier (PA) on the transmitter side. This work shows that by employing a suitable design methodology, a single dual-function amplifier can be realised which meets the required performance specification. In this way, power consumption and chip area can both be reduced, leading to cost savings so vital to the widespread utilisation of the ZigBee standard. Given the importance of device nonlinearity in such a design, a new transistor model based on independent representation of each of the transistor’s nonlinear elements is developed with the aim of quantifying the individual contribution of each of the transistors nonlinear elements, to the total distortion. The methodology to the design of the dual functionality (LNA/PA) amplifier starts by considering various low noise amplifier architectures and comparing them in terms of the trade-off between noise (required for LNA operation) and linearity (important for PA operation), and then examining the behaviour of the selected architecture (the common-source common-gate cascode) at higher than usual input powers. Due to the need to meet the far apart performance requirements of both the LNA and PA, a unique amplifier design methodology is developed The design methodology is based on simultaneous graphical visualisation of the relationship between all relevant performance parameters and corresponding design parameters. A design example is then presented to demonstrate the effectiveness of the methodology and the quality of trade-offs it allows the designer to make. The simulated performance of the final amplifier satisfies both the requirements of ZigBee’s low noise and power amplification. At 2.4GHz, the amplifier is predicted to have 1.6dB Noise Figure (NF), 6dBm Input-referred 3rd-order Intercept Point (IIP3), and 1dB compression point of -3.5dBm. In low power operation, it is predicted to have 10dB gain, consuming only 8mW. At the higher input power of 0dBm, it is predicted to achieve 24% Power-Added Efficiency (PAE) with 8dB gain and 22mW power consumption. Finally, this thesis presents a set of future research proposals based on problems identified throughout its development.

<p>Developing an automatic control system from original stage is quite time consuming, a lot of works must be done before the final result, in order to save designing time and money, a systematic way to carry through development is necessary. This project will give an experience about using a systemic method to develop an automatic control system for metal dosing and transfer from original stage. The project will be divided into several different phases, and each phase focuses on some different important tasks. In this project a research of PLCs and stepper motors and then give suitable suggestions of selection of them have been done. One of important roles for this project is to develop a prototype machine and use computer to model and simulate prototype and whole machine, therefore, in this project, using SDL assistant with Matlab to model and simulate both prototype and whole machine have been processed. Because of some unexpected condition, this project doesn’t include real PLC programming.</p>

Advances in transistors with cut-off frequencies >400GHz have fuelled interest in security, imaging and telecommunications applications operating well above 100GHz. However, further development of passive networks has become vital in developing such systems, as traditional coplanar waveguide (CPW) transmission lines, the most fundamental passive component, exhibit high losses in the millimetre and sub-millimetre wave regime. This work investigates novel, practical, low loss, transmission lines for frequencies above 100GHz and high-Q passive components composed of these lines. At these frequencies, transmission line losses are primarily due to the influence of the waveguide substrate. We therefore focus on structures which elevate transmission line traces above the substrate using air-bridge technology. Thorough analysis is performed on a range of elevated structures, and analytic / semi-analytic formulae for component figures of merit obtained. These, along with comprehensive 2 and 3D simulations are used to design discrete lines and distributed passive networks, with a focus on the 140-320 GHz frequency range. Innovative fabrication and detailed characterisation of the components are also carried out. The key result is the development of a novel MMIC compatible transmission line structure, Elevated-Grounded CPW, with a relatively simple fabrication process. EGCPW provides high substrate isolation, resulting in a low losses and high-quality passive networks. 50Ω EGCPW transmission line shows an insertion loss of 2.5dB/mm at 320GHz, 2.5dB/mm less than CPW. EGCPW passive networks, including resonators and filters, show higher performance than both conventional CPW and other forms of elevated CPW. 30-80% improvements in quality factor are shown, and an EGCPW band-pass filter with the centre frequency of 220GHz shows a 12% reduction in bandwidth and 4.5dB reduced in-band loss compared with its CPW counterpart. Due to the superior performance of MMIC-compatible EGCPW, as well as its ability to support a wide range of characteristic impedances, this structure is suggested as a candidate for widespread use in sub-millimetre wave circuits in order to increase efficiency and reduce losses.

Early signs of intestinal cancer may be detected through variations in tissue autofluorescence (AF), however current endoscope-based AF systems are unable to inspect the small intestine. This thesis describes the design, fabrication, implantation, testing and packaging of a wireless pill capable of detecting the autofluorescence from cancerous cells, and able to reach parts of the gastrointestinal tract that are inaccessible to endoscopes. The pill exploits the fact that there is a significant difference in the intensity of autofluorescence emitted by normal and cancerous tissues when excited by a blue or ultra violet light source. The intensity differences are detected using very sensitive light detectors. The pill has been developed in two stages. The first stage starts with using an off-chip multi-pixel photon counter (MPPC) device as a light detector. In the second stage, the light detector is integrated into an application specific integrated circuit (ASIC). The pill comprises of an ASIC, optical filters, an information processing unit and a radio transmission unit, to transmit acquired data to an external base station. Two ASICs have been fabricated, the first stage of this work involved implementing an ASIC that contains two main blocks; the first block is capable of providing a variable DC voltage more than 72 V from a 3 V input to bias the MPPC device. The second main block is a front-end consisting of a high speed transimpedance amplifier (TIA) and voltage amplifiers to capture the very small current pulses produced by the MPPC. The second ASIC contains a high voltage charge pump up to (37.9 V) integrated with a single photon avalanche detector (SPAD). The charge pump is used to bias the SPAD above its breakdown voltage and therefore operate the device in Geiger mode. The SPAD was designed to operate in the visible region where its photon detection efficiency (PDE) peaks at 465 nm, which is near to human tissues autofluorescence peaking region (520±10 nm). The use of the ultra low light detector to detect the autofluorescence permits a lower excitation light intensity and therefore lower overall power consumption. The two ASICs were fabricated using a commercial triple-well high-voltage CMOS process. The complete device operates at 3V and draws an average of 7.1mA, enabling up to 23 hours of continuous operation from two 165mAh SR44 batteries.

The objective of this thesis is to present the design and implementation of ultra-low power radio transceivers at microwave frequencies, which are applicable to wireless sensor network (WSN) and, in particular, to the requirement of the Speckled Computing Consortium (or SpeckNet). This was achieved through quasi-MMIC prototypes and monolithic microwave integrated circuit (MMIC) with dc power consumption of less than 1mW and radio communication ranges operating at least one metre. A wireless sensor network is made up of widely distributed autonomous devices incorporating sensors to cooperatively monitor physical environments. There are different kinds of sensor network applications in which sensors perform a wide range of activities. Among these, a certain set of applications require that sensor nodes collect information about the physical environment. Each sensor node operates autonomously without a central node of control. However, there are many implementation challenges associated with sensor nodes. These nodes must consume extremely low power and must communicate with their neighbours at bit-rates in the order of hundreds of kilobits per second and potentially need to operate at high volumetric densities. Since the power constraint is the most challenging requirement, the radio transceiver must consume ultra-low power in order to prolong the limited battery capacity of a node. The radio transceiver must also be compact, less than 5×5 mm2, to achieve a target size for sensor node and operate over a range of at least one metre to allow communication between widely deployed nodes. Different transceiver topologies are discussed to choose the radio transceiver architecture with specifications that are required in this project. The conventional heterodyne and homodyne topologies are discussed to be unsuitable methods to achieve low power transceiver due to power hungry circuits and their high complexity. The super-regenerative transceiver is also discussed to be unsuitable method because it has a drawback of inherent frequency instability and its characteristics strongly depend on the performance of the super-regenerative oscillator. Instead, a more efficient method of modulation and demodulation such as on-off keying (OOK) is presented. Furthermore, design considerations are shown which can be used to achieve relatively large output voltages for small input powers using an OOK modulation system. This is important because transceiver does not require the use of additional circuits to increase gain or sensitivity and consequently it achieves lower power consumption in a sensor node. This thesis details the circuit design with both a commercial and in-house device technology with ultra-low dc power consumption while retaining adequate RF performance. It details the design of radio building blocks including amplifiers, oscillators, switches and detectors. Furthermore, the circuit integration is presented to achieve a compact transceiver and different circuit topologies to minimize dc power consumption are described. To achieve the sensitivity requirements of receiver, a detector design method with large output voltage is presented. The receiver is measured to have output voltages of 1mVp-p for input powers of -60dBm over a 1 metre operating range while consuming as much as 420μW. The first prototype combines all required blocks using an in-house GaAs MMIC process with commercial pseudomorphic high electron mobility transistor (PHEMT). The OOK radio transceiver successfully operates at the centre frequency of 10GHz for compact antenna and with ultra-low power consumption and shows an output power of -10.4dBm for the transmitter, an output voltage of 1mVp-p at an operating range of 1 metre for the receiver and a total power consumption of 840μW. Based on this prototype, an MMIC radio transceiver at the 24GHz band is also designed to further improve the performance and reduce the physical size with an advanced 50nm gate-length GaAs metamorphic high electron mobility transistor (MHEMT) device technology.

Multilevel converters have attracted a great deal of interest in recent years since they offer a number of advantages in many high voltage and high power applications, such as adjustable speed electric motor drives and power systems through Flexible Alternating Current Transmission Systems (FACTS) controllers and active harmonic filters. They can reach high voltages with low harmonics without the use of transformers or series-connected synchronised switching devices by their unique structures. Along with proper Pulse-Width Modulation (PWM) control scheme, they can also provide lower cost, higher performance, lower Electro-Magnetic Interference (EMI), and higher efficiency than the traditional PWM converters. However, switching losses become a serious issue in high power applications. In order to improve the efficiency and reliability of the system, and reduce the size of the output filter, the stresses on the semiconductors and the development and manufacturing costs, reducing the switching frequency and associated losses of multilevel PWM converters and systems needs to be properly addressed. The thesis gives an overview on multilevel converter topologies and control schemes. It then presents mathematical analysis towards further understanding of the Neutral-Point-Clamped (NPC) and the Flying Capacitor (FC) converters. The Fundamental Frequency Sinusoidal PWM (FF-SPWM) control method is examined as a potential "carrier" based approach in reducing the converter switching frequency and associated losses. The performance of multi-modular parallel connected systems based on the NPC and FC converters as a building block is reported along with the influence of the multicarrier PWM techniques. The voltage-unbalancing problem of the FC converter is addressed and a solution is provided. DSP based controllers for the three-level and the five-level FC converters have been developed and experimentally verified. Results taken from the laboratory prototype are presented to support the theoretical part of the project.

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface.

This thesis describes the reliable design of tunnel diode and resonant tunneling diode (RTD) oscillator circuits. The challenges of designing with tunnel diodes and RTDs are explained and new design approaches discussed. The challenges include eliminating DC instability, which often manifests itself as low frequency parasitic oscillations, and increasing the low output power of the oscillator circuits. To stabilise tunnelling devices, a common but sometimes ineffective approach is the use of a resistor of suitable value connected across the device. It is shown in this thesis that this resistor tunnel diode circuit can be described by the Van der Pol model. Based on this model, design equations have been derived which enable the design of current-voltage (I-V) measurement circuits that are free from both low frequency bias oscillations and high frequency parasitic oscillations. In the conventional setup, the I-V characteristic of the tunnelling device is extracted from the measurement by subtracting from the measured current the current through the stabilising resistance at each bias voltage. In this thesis, also using the Van der Pol model, a circuit for the direct measurement of I-V characteristics is proposed. This circuit utilises a series resistor-capacitor combination in parallel with the tunnelling device for stabilisation. Experimental results show that IV characterisation of tunnel diodes in the negative differential resistance (NDR) region free from oscillations can be made. A new test set-up suitable for radio frequency (RF) characterisation of tunnel diodes over the entire NDR region was also developed. Initial measurement results on a packaged tunnel diode indicate that accurate characterisation and subsequent small-signal equivalent circuit model extraction for the NDR region can be done. To address the limitations of low output power of tunnel diode or RTD oscillators, a new multiple device circuit topology, incorporating a novel design methodology for the DC bias decoupling circuit, has been developed. It is based on designing the oscillator specifically for sinusoidal oscillations, and not relaxation oscillations which are also possible in tunnel diode oscillators. The oscillator circuit can also be described by the Van der Pol model which provides theoretical predictions of the maximum inductance, in terms of the tunnel diode device parameters, that is required to resonate with the device capacitance for sinusoidal oscillations. Each of the tunnel diodes in the multiple device oscillator circuit is decoupled from the others at DC and so can be stabilised independently. The oscillator topology uses parallel resonance but with each tunnel diode individually biased and DC decoupled making it possible to employ several tunnel diodes for higher output power. This approach is expected to eliminate parasitic bias oscillations in tunnel diode oscillators whilst increasing the output power of a single oscillator. Simulation and experimental oscillator results were in good agreement, with a two-tunnel diode oscillator exhibiting approximately double the output power as compared to that of a single tunnel diode oscillator, i.e. 3 dB higher. Another method considered for the realisation of higher output power tunnel diode or RTD oscillators was series integration of the NDR devices. A new method to suppress DC instability of the NDR devices connected in series with all the devices biased in their NDR regions was investigated. It was successfully employed for DC characterisation with integrations of 2 and 5 tunnel diodes. Even though no suitable oscillator circuit topology and/or methodology with series-connected NDR devices could be established for single frequency oscillation, the achieved results indicated that this approach may be worthy of further investigation. The final aspect of this project focussed on the monolithic realisation of RTD oscillators. Monolithic oscillators in coplanar waveguide (CPW) technology were successfully fabricated and worked at a fundamental frequency of 17.5 GHz with -21.83 dBm output power. Finally, to assess the potential of RTD oscillators for high frequency signal generation, a theoretical analysis of output power of stabilised RTD oscillators was undertaken. This analysis suggests that it may be possible to realise RTD oscillators with high output power (0 dBm) at millimetre-wave and low terahertz (up to 1 THz) frequencies.

The ultrashort pulses emitted by passive semiconductor mode-locked lasers (PSMLLs) can be applied to a wide range of applications, including modern optical communication systems, optical sampling, security, imaging or sensing. For most of these applications, it is of critical importance to gather detailed information on the mode-locked laser (MLL) dynamics as well as on the temporal intensity and phase profiles of the pulses. The pulse formation in a PSMLL is in fact a very complex mechanism that is governed by the close interplay between a number of linear and nonlinear phenomena, influenced by various semiconductor parameters. The complete characterisation of the devices as a function of the laser driving parameters, geometry and semiconductor material structure has therefore the potential to provide a deeper understanding of the PSMLL behaviour. As the available detectors are usually incapable of resolving the temporal structures of ultrashort pulses from the high repetition rate MLLs, a number of indirect measurement solutions have been developed for full pulse characterisation. However, these methods are designed for lasers with high-energy optical pulses or require pulse synchronisation or ultrafast modulation. This obviously restricts their suitability for the unsynchronised, low energy and high repetition rate pulses as those emitted by the mode-locked laser diodes. In this work, an extensive study of various dynamical regimes, such as mode-locking, self-pulsation and continuous-wave operations of the monolithically integrated AlGaInAs/InP MLLs is reported. The devices operate around 1.55 µm and emit optical pulses with sub-40 GHz repetition frequencies. The influence of the biasing conditions, laser geometry and semiconductor material on the lasers performance is analysed in detail. The complete characterisation includes the evaluation of both the phase and time profiles of pulses, using a sonogram system developed as part of this thesis. It is based on a self-referenced method, capable of ambiguity-free measurements of low power and sub-picosecond pulses. A sensitivity as low as 5mW on the pulse peak power has been achieved through the design and fabrication of a two-photon absorption (TPA) detector, optimised for polarisation insensitivity and high nonlinear response. The travelling-wave operation enables the characterisation of high-repetition rate pulses and minimises the amount of introduced dispersion. The sonogram system has been successfully employed to study the evolution of the temporal intensity and group delay profiles as a function of the laser biasing conditions and for different device geometries. The obtained results indicate a prevailing positive chirp present in the pulses, which can be reduced by a careful adjustment of the device biasing. The minimum pulse width emitted from the investigated MLLs and measured with the sonogram technique was ~500 fs.

Analog-to-digital converters play a crucial role in modern audio and communication design. Conventional Nyquist converters are suitable only for medium resolutions and require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can achieve high resolutions (>20bits) and can be implemented using straightforward, high-tolerance analog components. In conventional oversampled modulators, negative feedback is applied in order to control the dynamic behavior of a system and to realize the attenuation of the quantization noise in the signal band due to noise shaping. However, feedback can also introduce undesirable effects such as limit cycles, jitter problems in continuous-time topologies, and infinite impulse responses. Additionally, it increases the system complexity due to extra circuit components such as nonlinear multi-bit digital-to-analog converters in the feedback path. Moreover, in certain applications such as wireless, biomedical sensory, or microphone implementations feedback cannot be applied. As a result, the main goal of this thesis is to develop sigma-delta data converters without feedback. Various new delta-sigma analog-to-digital converter topologies are explored their mathematical models are presented. Simulations are carried out to validate these models and to show performance results. Specifically, two topologies, a first-order and a second-order oscillator-based delta-sigma modulator without feedback are described in detail. They both can be implemented utilizing VCOs and standard digital gates, thus requiring only few components. As proof of concept, two digital microphones based on these delta-sigma converters without feedback were implemented and experimental results are given. These results show adequate performance and provide a new approach of measuring.