As the current electronic trend is toward integrating multiple functions in a single electronic device, there is a clear need for increasing integration density which is becoming more emphasized than in the past. To meet the industrial need and realize the new system-integration law [1], three-dimensional (3-D) integration is becoming necessary. 3-D integration of multiple functional IC chip/package modules requires co-simulation of the chip and the package to evaluate the performance of the system accurately. Due to large scale differences in the physical dimensions of chip-package structures, the chip-package co-simulation in time-domain using the conventional FDTD scheme is challenging because of Courant-Friedrich-Levy (CFL) condition that limits the time step. Laguerre-FDTD has been proposed to overcome the limitations on the time step. To enhance performance and applicability, SLeEC methodology [2] has been proposed based on the Laguerre-FDTD method. However, the SLeEC method still has limitations to solve practical 3-D integration problems. This dissertation proposes further improvements of the Laguerre-FDTD and SLeEC method to address practical problems in 3-D interconnects and 3-D integration. A method that increases the accuracy in the conversion of the solutions from Laguerre-domain to time-domain is demonstrated. A methodology that enables the Laguerre-FDTD simulation for any length of time, which was challenging in prior work, is proposed. Therefore, the analysis of the low-frequency response can be performed from the time-domain simulation for a long time period. An efficient method to analyze frequency-domain response using time-domain simulations is introduced. Finally, to model practical structures, it is crucial to model dispersive materials. A Laguerre-FDTD formulation for frequency-dependent dispersive materials is derived in this dissertation and has been implemented.

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