Plume location and prediction using mobile sensors is the main contribution of this thesis. Plume concentration values measured by chemical sensors at different locations are used to estimate the source of the plume. This is achieved by employing a stochastic approximation technique to localize the source and compare its performance to the nonlinear least squares method. The source location is then used as the initial estimate for the boundary tracking problem. Sensor measurements are used to estimate the parameters and the states of the state space model of the dynamics of the plume boundary. The predicted locations are the reference inputs for the LQR controller. Measurements at the new locations (after the correction of the prediction error) are added to the set of data to refine the next prediction process. Simulations are performed to demonstrate the viability of the methods developed. Finally, interpolation using the sensors locations is used to approximate the boundary shape.

Positron Emission Tomography (PET) has been a very useful laboratory tool for the noninvasive study of dynamic physiological processes within the human body. Its clinical worth in cardiology, neurology, and oncology has been verified for well over a decade. Only with the most recent introduction of high performance analog and VLSI digital components yielding higher scanner resolutions at reduced costs, has clinical PET truly become a reality. The High Performance Detector Electronics System presented here represents indubitably the most advanced processing system available in the clinical PET market.

In this work the design of a constant-fraction discriminator (CFD) fabricated in the Orbit Semiconductor l.2-Jl n-well CMOS process is presented. This timing pick-off circuit is designed for use in the readout electronics of the Lead-Scintillator subsystem of the Pioneering High Eenergy Nuclear Ion eXperiment (PHENIX) Electromagnetic Calorimeter at the Relativistic Heavy Ion Collider (RHIC). The design was driven by stringent requirements including low power consumption, small area, arrayable, low cost and a fully integratable shaping network. Various integratable CFD shaping methods are investigated, and the candidate methods chosen for fabrication were the distributed R-C delay-line shaping, lumped-element R-C shaping and Nowlin method shaping. An additional channel of ideal delay-line shaping, utilizing coaxial cable to generate delay, was fabricated and used for a reference in comparing methods. These shaping methods are compared on the basis of die area, time walk performance and timing jitter performance as implemented using the CMOS CFD presented. Each shaping method investigated required no power from the dc supply. Die area for the distributed R-C delay-line, lumped-element R-C, Nowlin method and ideal delay-line (fraction circuit only) were 172 Jl X 70 Jl, 160 Jl X 65 Jl, 179 Jl X 53 Jl and 67 Jl X65Jl,respectively. Timewalkovera100:1dynamicrange(-2Vpeakto-20mVpeak) for these shaping methods in turn was found to be ± 175 ps, ± 150ps , ± 150 ps and ± 185 ps, respectively. Timing jitter performance with a minimum input signal (-20 mVpeak) in rms units for the four methods in turn were 65 ps, 85 ps, 100 ps and 65 ps. The average power dissipated per CFD channel was found to be approximately 12 mW.

The aerodynamic applications of plasma science is a field of growing interest. Investigations using various approaches have been initiated by several research groups that are designed to manipulate the aerodynamic boundary layer and to re-attach the flow to airfoils. EHD (ElectroHydroDynamic) flow control has proven at least as effective as other methods of boundary layer flow control. In the EHD approach, glow discharge plasma actuators are placed on the wings and fuselage of the aircraft, or on the turbine blades in the engine, to influence the boundary layer flow. This thesis is concerned with plasma actuators based on the OAUGDP ® (One Atmosphere Uniform Glow Discharge Plasma). An actuator consists of two conducting electrodes separated by a dielectric plate. When a sufficiently high RF voltage is supplied to the electrodes, the surrounding air ionizes and forms plasma in regions in which the electric field is above approximately 10 kV/cm. The ionized air, in the presence of an electric field gradient, produces a body force on the neutral gas flow.This work is concerned with two EHD effects: paraelectric flow acceleration and peristaltic flow acceleration. In the paraelectric mode, electric field gradients act on the net charge density of plasma, and the plasma drags the neutral gas along with it due to ion-neutral and electron-neutral Lorentzian collisions. In the peristaltic mode, successive actuators are energized with the same voltage, but increasing phase angles. The first part of this thesis describes experiments at the NASA Langley Research Center, Hampton, VA in the 7 x 11 Inch Low Speed Wind Tunnel in which Pitot tube velocity profile measurements and smoke flow visualization tests were conducted.The second part of this thesis describes the development of a low cost power supply to energize OAUGDP ® plasma actuators. The power supply consists of automotive ignition coil transformers, audio amplifiers, and a DC battery. Using this power supply, plasma actuators were energized at voltages up to 8 kV, and at frequencies between 0.5 and 8 kHz. This thesis also presents illustrative paraelectric flow acceleration data obtained using the low-cost power supply.

The advances in VLSI and packaging technologies enable us to integrate a whole system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to explore the new design space and opportunities for System-on-Package (SoP), with special attention on radio and mixed-signal system applications. Global level system partitioning for SoC and SoP with cost-performance trade-off, concurrent chip and design for high-speed off-chip signaling, global clock distribution, and ultra wideband (UWB) radio module are two fields in this research. Cost-performance driven for mixed-signal system partitioning in early conceptual level design is first addressed in this thesis. We develop a modeling technique to pre-estimate the cost and performance. The performance model evaluates various noise isolation technologies, such as using guard rings, and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, is developed for cost estimation under various mixed-signal performance constraints. System interconnect topologies have been moving away from multi-point bus architecture and towards high-speed serial links. But low interaction between chip and package design has more and more limited system performance. We address concurrent chip and package design and co-optimization for high-speed off-chip signaling in this part. First we explore the interconnect and package constraints to the circuit and system architecture. Proper equivalent circuit models for package parasitics are set up and then a 3-dimension electromagnetic (EM) solver is used to extract the parasitic parameters of package. After that, bandwidth and noise of the signal channel are estimated. The optimal off-chip singling is designed according to these packages and interconnection constraints. We also analyzed the global clock distribution using co-design method. We developed a low cost, low power consumption, and low complexity UWB radio module using co-design method and SoP technologies. The module will be used in low data rate and long-range wireless intelligent systems such as radio frequency identification (RFID) or wireless sensors networks (WSN). Liquid-crystal-polymer (LCP) based SoP technologies were used to implement the module. / <p>QC 20101006</p>

In line with the quality awareness of good prevention of pressure sores and in treatment of those sores already developed, evaluation of antidecubitus mattresses plays an important role. However, there are shortages in the evaluations performed today, since often interface pressure is the only parameter regarded. Since ischaemia in the tissue is the primary cause of pressure sore, the focus in this thesis is on blood flow measurements in tissue exposed external loading. To study the tissue blood flow would give a better and more direct indication on the mattress effectiveness in minimizing the negative effects on the tissue viability. The results presented in this thesis reveal that the superficial blood flow in areas prone to pressure sore development, is affected by increased skin temperature and external loading of the tissue. Both the effects from pressure and shear stress have been studied. Measurements of the tissue blood flow is interesting to relate to the two theories about at which tissue layer the pressure sores start to develop. To achieved more knowledge about the pressure sore etiology and also be able to non-invasively measure the tissue blood flow for evaluations of antidecubitus mattresses an optical sensor has been developed. The sensor combines the two optical methods, laser Doppler flowmetry and photoplethysmography. With the design of the sensor, measurements of the superficial skin blood flow and the deeper blood flow, even the muscle blood flow, can be performed. Measurement depths of 2 mm, 8 mm, and 20 mm into the tissue is assumed. Preliminary result from measurements performed with the optical sensor in four test subjects, revealed great individual differences in blood flow, but also different response to the same external loading at different measurement depths, in the same individual. This new optical sensor is likely to be of great value in future studies of pressure sore etiology and in future evaluations of antidecubitus mattresses.

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance. Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components. / Sensible Things That Communicate

In this thesis, digit-serial implementation of recursive digital filters is considered. The theories presented can be applied to any recursive digital filter, and in this thesis we study the lossless discrete integrator (LDI) allpass filter. A brief introduction regarding suppression of limit cycles at finite wordlength conditions is given, and an extended stability region, where the second-order LDI allpass filter is free from quantization limit cycles, is presented. The realization of digit-serial processing elements, i.e., digit-serial adders and multipliers, is studied. A new digit-serial hybrid adder (DSHA) is presented. The adder can be pipelined to the bit level with a short arithmetic critical path, which makes it well suited when implementing high-throughput recursive digital filters. Two digit-serial multipliers which can be pipelined to the bit level are considered. It is concluded that a digit-serial/parallelmultiplier based on shift-accumulation(DSAAM) is a good candidate when implementing recursive digital systems, mainly due to low latency. Furthermore, our study shows that low latency will lead to higher throughput and lower power consumption. Scheduling of recursive digit-serial algorithms is studied. It is concluded that implementation issues such as latency and arithmetic critical path are usually required before scheduling considerations can be made. Cyclic scheduling using digit-serial arithmetics is also considered. It is shown that digit-serial cyclic scheduling is very attractive for high-throughput implementations.

Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked Loop (PLL) frequency synthesizers are found in most modern radio transceivers. All practical PLL implementations suffer from unwanted frequency components such as phasenoise and spurious tones, and since these components affect system performance they must be predicted and minimized. This thesis discuss the design and implementation of fully integrated PLL circuits. Techniques to predict system performance are investigated. The strongly non-linear operation of PLL building blocks are analyzed, using both analytical and numerical methods. Techniques to reduce impact of interferer down-conversion and noise folding are suggested. Methods to perform automatic calibration in order to make circuits less sensitive to process variations are proposed. The techniques are verified through a number of PLL implementations. The design and implementation of a transceiver targeting a dual band IEEE 802.11 a/b/g wireless LAN operation is discussed. The circuit use two PLL:s operating at 1310 to 1510 MHz and 3.84 GHz respectively. Noise contributions of various PLL building blocks and their impact on over all system performance are analyzed. The combined integrated phase noise is below -34 dBc, and measured transceiver Error Vector Magnitude (EVM) is better than 2.5 dB in both the 2.4 and 5 GHz bands. A low power frequency synthesizer targeting Frequency Shift Keying applications such as ZigBee and BlueTooth is presented. The synthesizer use open-loop direct modulation of the carrier, but unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. This allows the use of a small area on-chip loop filter without violating noise or spurious requirements. To handle the frequency drift normally associated with open-loop implementations, a low-leakage charge-pump is proposed. The synthesizer is implemented using a 0.18μm CMOS process. Total power consumption is 9 mW and the circuit area including the VCO inductors and on-chip loopfilter is 0.32mm2. Measured leakage current is less than 2 fA. A small area amplitude detector circuit is proposed. The wide-band operation and small input capacitance make the circuit suitable for embedding in an RF system on-chip, allowing measurement of on-chip signal levels and automatic calibration. Finally an oscillator topology reducing the phase noise in voltage controlled oscillators is suggested. By using on-chip decoupling and an amplitude control circuit to adjust oscillator bias, the impact of current source noise is eliminated. The theoretical phase noise is reduced 3.9 dB compared to a conventional LC oscillator using the same bias current. / QC 20100817

The topic of this dissertation is divided into two parts where the first part presents high-speed data transmission on flexible cables and the second part presents a wireless remote monitoring and controlling system with wireless data transmission. The demand on high-speed data communications has pushed both the wired and wireless technologies to operate at higher and higher frequencies. Classic Kirchhoff’s voltage and current laws cannot be directly applied, when entering the microwave spectrum for frequency above 1 GHz. Instead, the transmission line theory should be used. Most of the wired communication products use bit-serial cables to connect devices. To transfer massive data at high speed, parallel data transfer techniques can be utilized and the speed can be increased by the number of parallel lines or cables, if the transfer rate per line or cable can be maintained. However, the lines or cables must be well-shielded so the crosstalk between them can be minimized. Differential lines can also be used to increase the data speed further compared to the single-ended lines, along with saving the power consumption and reducing the electromagnetic interference. However, characterization for differential lines is not as straight forward as for single-ended cases using standard S-parameters. Instead, mixed-mode S-parameters are needed to describe the differential-, common- and mixed-mode characteristics of the differential signal. Mixed-mode S-parameters were first introduced in 1995 and are now widely used. However, improvements of the theory can still be found to increase the accuracy of simulations and measurements, which is proposed and presented in this dissertation. The interest of wireless solution to do remote control and monitoring for cultural building has been increasing. Available solutions on the market are mostly wired and very expensive. The available wireless solutions often offer limited network size with point-to-point radio link. Furthermore, the wired solution requires operation on the building, which is not the preferred way since it will damage the historical values of cultural heritage buildings. Wireless solutions on the other hand can offer flexibility when deploying the network, i.e., operation on the building can be avoided or kept to the minimum. A platform for wireless remote monitoring and control has been established for various deployments at different cultural buildings. The platform has a modular design to ease future improvement and expansion of the system. The platform is based on the ZigBee standard, which is an open standard, specified with wireless sensor network as focus. Three different modules have been developed. The performance has been studied and optimized. The network has been deployed at five different locations in Sweden for data collection and verification of the system stability. The remote monitoring and control functions of the developed platform have received a nomination for the Swedish Embedded Award 2010 and been demonstrated at the Scandinavia Embedded Conference 2010 in Stockholm.Communication