Cartographic compilation requires precision mensuration. The calibration of mensuration processes is based on specific fiducials. External fiducials, around the exterior frame of the image, must be precisely measured to establish the overall physical geometry. Internal fiducials are provided within the image by placement of cloth panels on the ground at locations whose position is precisely known. Both types of fiducials must be known within the pixel space of a digitized image in order for the feature extraction process to be accurate with respect to delineated features. Precise mensuration of these fiducials requires that a cartographer view the image on a display and use pointing devices, such as a mouse, to pick the exact point. For accurate fiducial location, the required manual operations can be an added time-consuming task in the feature extraction process. Interactive tools which eliminate the precise pointing action for the operator are described in this thesis. The operator is required only to "box-in" the fiducial, using a simple drawing tool, select the fiducial function, and the software of the tool returns the precise location of the fiducial.

The University of Arizona Campus Internet consists of numerous Local Area Networks (LANs) attached to an Ethernet backbone. Any campus LAN which cannot interconnect with this backbone is effectively isolated. The generic gateway project was conceived to research and develop gateway systems which will help incorporate new LANs into the campus internet. The work presented here is the design, development, implementation and testing of a gateway for a selected campus LAN. The candidate LAN which was selected was the University of Arizona Sytek broadband network, which includes the Sytek LocalNet 20 and System 2000 networks.

Multiprocessor networks are widely used in the design of computer systems and telecommunication systems nowadays. And multistage interconnection networks (MINs) provide desirable high-performance and reliable interconnections, which are required in multiprocessor networks, between its processing elements (PEs) and/or memory modules (MMs). In this thesis, the augmented shuffle-exchange network (ASEN), which is a fault-tolerant MIN scheme, will be modified so as to address the problem of multi-input conflicts existing with the original proposed network scheme. The modification of ASEN has two parts. The first part is the modification of the structure of ASEN. And the second part is the development of new routing algorithm for the modified ASEN. Experimental results are provided to show that the modified augmented shuffle-exchange network (MASEN) proposed is able to enhance the MIN's ability to resolve the conflicts between multiple inputs when they occur, and the complexity of MASEN remains the same as in ASEN.

The Abel inversion is used to reconstruct an axisymmetric image from a one-dimensional projection. It finds application in a wide variety of fields, such as astronomy, optical-fiber refractive-index measurements and spray-droplet studies where the geometry is often cylindrically or spherically symmetric. However, all Abel inversion methods have drawbacks. One such arises from the singularity in the lower limit of the integral. The smoothing techniques also usually consume a large amount of computer time and the error propagation calculations are tedious. Two methods with a different approach are presented in this thesis. They are the Integral transforms and the onion-peeling method. They are both easier and simpler to compute. Also, no curve fitting is needed and the problem of handling the singularity will not arise. The noise and artifact properties of these two methods are investigated.

This thesis investigates the effects of ionizing radiation on the noise properties of n-channel power DMOS transistors. The pre-irradiation noise power spectral density of these transistors was found to vary as 1/ flambda where lambda (the slope of the noise power spectral density when plotted on a log-log scale) ranged from approximately 0.5 to 1.0. Radiation-induced trapped charge density was found to have a large effect on the magnitude and slope of the noise. Irradiation of devices was found to produce a more uniform distribution in time constants leading to the more ideal 1/f noise power spectrum as total dose increased. Polarity of bias applied during post-radiation anneal was found to force a distribution in time constants leading to an increase in lambda for devices under negative gate bias and a decrease in lambda for devices under positive gate bias. Radiation hardness of power MOSFETs was investigated as a function of their pre-irradiation 1/f noise. No correlation was found between noise magnitude and device hardness.

The Solar potential is studied, at the synoptical scale (Senegal-West Africa) via a set of terrestrial measurements of the sunshine duration, the insolation, the ambient temperature and the wind speed. First the missing data have been estimated (in Time and Space) via the study of the data structure and by use of a reconstitution formula derived from Correspondence Analysis. Then a geostatistical approach has been used to analyze a sufficiently long series of data to characterize statistically the climatological behavior of the Insolation in Space over the support defined above. Hence, the steps of deriving maps of isopleths for sparse Space and Time-series measurements of a given support will be presented. The possible applications are the cartography or simulation of fields, the optimization of measurement stations, the design of Solar equipments and the analysis of remote sensing data.

Faults on power distribution systems can be prevented quickly and reliably by using solid-state devices to coordinate the optimum functioning and operation of the distribution system. This thesis describes specific systems and circuits designed for this purpose. Some parts employed in the isolation of faults are: sensors, quadrature amplitude modulators, fiber optic cables, programmable logic controllers, generators, band pass filters and silicon controlled rectifiers. Design information and test data are presented.

The demand for maps and related cartographic products has increased greatly over the past years. This increase in the demand for cartographic products has greatly increased the work load for the cartographer because current practice requires the cartographer to manually identify and delineate the significant cartographic features from an image. The availability of digital image data has made it possible to use the computer to assist in the extraction and delineation of cartographic features. This research presents one approach to automating the delineation of large area features using neural networks for texture pattern classification.

The focus of this thesis is the computation of bit error rate in an optical fiber communication system when an avalanche photodiode (APD) is used for detection. The use of the APD increases the complexity of the BER calculation because it introduces an additional noise phenomenon: shot noise (plus multiplication noise). There are several methods to compute the BER. This thesis considers three of these methods: the Gaussian approximation, the saddlepoint approximation and a numerical quadrature method. An in-depth analysis of each computation method is presented after a thorough study of APD characteristics, involving its probability density function and its moment generating function. Numerical examples are shown and compared for each method. The examples show that the saddlepoint approximation method can be used to provide an accurate, simple form for the bit error rate, and that the Gaussian approximation tends to underestimate the BER at high gains. Different results with different photodetectors are illustrated throughout the thesis for a better understanding.

Hardware description languages can be powerful tools in creating digital system designs. AHPL, A Hardware Programming Language, is a hardware description language that simplifies the task of designing a digital system. One of the major problems in using a hardware description language is interfacing with commercially available simulation and layout tools. Many commercial tools use the Electronic Design Interchange Format (EDIF) in order to communicate designs. This thesis describes the AHPL to EDIF Netlist Translator (AENT) program. By using AENT, a designer can write an AHPL description, verify the design with a function level simulator, and generate a CMOS standard cell layout using a commercial layout tool. A post layout gate level simulation can also be performed to verify timing constraints. Several layout examples are given in this thesis, and results are compared with the Berkeley Synthesis System.