In this thesis, a system to locate an electrostatic discharge (ESD) event within an electronic device has been developed. ESD can cause a device to fail legally required radiated emissions limits as well as disrupt intended operation. The system used a fast oscilloscope with four channels, each channel attached to a high frequency near-field antenna. These antennas were placed at known locations in three dimensional space to measure the fields radiated from the ESD event. A Time-Difference-of-Arrival technique was used to calculate the location of the ESD event. Quick determination of the ESD event location provides developers with a tool that saves them time and money by eliminating the time-consuming and tedious method of general ESD mitigation within a product.

First, one of the purposes of this thesis is to estimate the complete crosstalk effects including the package and the pads on the surface acoustic wave (SAW) substrate. A new approach based on finite-difference time-domain (FDTD) with equivalent current source method is applied. Two kinds of patterns of one-port SAW resonators with the same package structure and inter-digital transducer (IDT) design are studied. Verification with the measurement results shows that our method is able to obtain good agreement and be used to observe the influence from the SAW pattern. Second, the equivalent current source method is extended to model the excitation of human-body¡¦s electrostatic discharge (ESD) situations. The efficiencies of sacrificial electrodes are also discussed. Finally, a novel sacrificial electrode with fractal to protect SAW devices from ESD break is proposed. Comparing with traditional electrode, the simulation results show that fractal can improve the protective efficiency greatly. Finally, a novel analysis model that can be used to analyze and optimize the impedance of an RFID transponder integrated circuit (IC) which uses backscatter encoding based on simultaneously maintaining the BER of the reader and maximizing the received power of the transponder IC is proposed. The analysis method utilizes mapping from signal constellation of the backscattered signal to the Smith chart to relate the two parameters. Given the system specification and characteristics of the reader and transponder antennas, the optimum impedances of transponder IC for binary communication system can be easily designed by using this model.

Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives.

Overcrowding during indoor events can be risky, in-case of any kind of a hazard such as fire.This solution address this by providing real-time crowd detection solution using Force-SensingResistor (FSR) sensors, referred sensor (IR) and microcontrollers. The solution needs to offer accurate data in real-time to the event managers including number of people and entrancerate to help when and if the event areas will be overcrowded, thereby enhancing event safetyand decision-making. This thesis indicate that the system offers essential real-time data forevent safety with an accuracy of 87.25%. These data will assists event managers in makinginformed decisions to avoid the risks of overcrowding. This thesis evaluates the effectivenessof our system in comparison to other systems, discussing what we’ve learned, suggest possibleimprovements, and talk about whether our system could be useful in real-world indoor events.