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Conception sur silicium de convertisseurs analogique-numérique haut débit pour le radiotélescope SKA / Design on silicon high speed analog-to-digital converters for the radio telescope SKADa Silva, Bruno 23 September 2010 (has links)
Pour les applications radioastronomiques, l'interface entre les mondes analogique et numérique est primordiale. Les convertisseurs analogique-numérique (CAN) doivent atteindre une forte résolution et un taux d'échantillonnage de plus en plus élevé pour numériser la plus grande bande passante possible. Pour le futur radiotélescope géant international SKA (Square Kilometer Array), la bande passante requise s'étend de 100 à 1500 MHz. L'objectif de ce mémoire est de concevoir et réaliser un CAN avec la technologie Qubic4X 0,25 µm en SiGeC, capable de dépasser le giga échantillon par seconde (GS/s) pour numériser toute la bande passante, pour des réseaux phasés denses. Deux études de CAN font l'objet de cette thèse. Dans le cadre de ce projet, nous avons analysé les différents blocs afin de minimiser les erreurs statiques et dynamiques pour une architecture parallèle 6 bits. Un premier CAN 6~bits en BiCMOS fonctionnant à une cadence de 1 GS/s a été étudié, réalisé et testé. Les simulations « post-layout » montrent un nombre de bits effectif de 4,6 bits pour une fréquence d'entrée de 400 MHz. La conception du masque permet de tester la puce. Ainsi, la sortie permet de valider le design. Les tests démontrent que le CAN opère à une fréquence maximale de 850 MS/s avec une bande passante de 400~MHz. Cependant, des erreurs persistent empêchant l'utilisation du circuit en raioastronomie. Le CAN consomme 2 Watts. Cette forte consommation est due aux interfaces d'entrées-sorties. Le second CAN bipolaire 6 bits fonctionne à une cadence de 3 GS/s. Ce convertisseur à architecture parallèle est entièrement conçu avec des topologies différentielles bipolaires. La partie numérique utilise une logique à émetteur couplé (ECL). Nous obtenons ainsi pour le second CAN une cadence de conversion élevée. Les simulations « post-layout » montrent que le CAN peut fonctionner à une fréquence de 3 GS/s, nous obtenons ainsi une bande passante de 1400 MHz. Les résultats dynamiques indiquent un nombre effectif de 5 bits pour une consommation de 3 Watts. / For applications in radio astronomy, the interface between the analog and digital domains is of primary concern. Analog-to-Digital Converters (ADC) must be capable of high resolution and extremely high sampling speeds in order to achieve the largest possible band width. For the future giant international radio telescope called the Square Kilometer Array (SKA), the bandwidth required is between 100 and 1500~MHz. The subject of the present thesis is to design and manufacture an ADC using the Qubic4X 0.25 µm technology in SiGeC capable of surpassing giga-samples per second (GS/s) in order to digitise the entire passband for dense phased-arrays. Two ADC designs are presented here. For this project, we analysed different design blocks with the goal of reducing static and dynamic errors in a 6-bit parallel architecture. The first 6-bit ADC which was designed, manufactured, and tested, was in BiCMOS and operated at 1 GS/s. The post-layout simulations showed the effective number of bits to be 4.6 bits with a 400 MHz input frequency. The mask design allowed for testing the chip. In this way, the output validates the design. Tests show that the ADC operates up to a maximum frequency of 850 MS/s with a passband of 400 MHz. However, there are some errors which make the current circuit unusable for astronomy purposes. The ADC runs on 2 Watts. The high power consumption is due to the input and output stages. The second 6-bit bipolar ADC operates at 3 GS/s. It is designed with a parallel architecture entirely using a bipolar differential topology. The digital part uses Emitter Coupled Logic (ECL). With this second chip, we obtain high speed conversion. Post-layout simulations show that the ADC can operate up to 3 GS/s, and we thus obtain a passband of 1400 MHz. Dynamic measurements indicate an effective number of bits of 5 bits with a power consumption of 3 Watts.
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A low ground bounce CMOS off-chip driver designZheng, Jieyin 04 August 1993 (has links)
With the advancement of technology, submicron CMOSonly process is available now for
Application Specific Integrated Circuits (ASICs). The high integration leads to the need for
high pin counts. However voltage supply and ground bounce due to many output drivers
switching at the same time is becoming a major problem. In this thesis, a CMOS offchip
buffer design which generates ECL logic levels with lower ground bounce noise is described
and demonstrated. The technique used in designing this buffer to reduce voltage
noise differs from conventional design techniques. Traditionally there are two general
methods to reduce ground bounce. One approach tries to reduce the instantaneous current
change (di/dt) by increasing (prolonging) the rise and fall time of the signals. The other approach
attempts to reduce the parasitic inductance attributed to packaging by using multiple
supply pins. Our technique reduces the voltage noise by controlling the instantaneous current
change through the reduction of current difference during switching time. Based on this
approach, a novel circuit structure is designed. This circuit has a fully symmetrical configuration
and is being selfbiased through negative feedback. A current injection technique is
also used to increase the stability of the circuit. SPICE simulation of the proposed circuit
is performed. Comparison and tradeoffs with other approaches are studied. / Graduation date: 1994
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Design considerations for high speed clock and data recovery circuits /Beshara, Michel, January 1900 (has links)
Thesis (M.App.Sc.) - Carleton University, 2002. / Includes bibliographical references (p. 93-95). Also available in electronic format on the Internet.
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