A 16-level instrument in which the input voltage is sampled and quantised to yield direct decimal readouts of 1/T∫v^2dt . and T is described. This is an improved version of an instrument previously constructed; The upper frequency limit has been extended from 5 Hz to about 2 kHz. The readout of the instrument can be in any code, the decimal code being implemented in the instrument described. The original error analysis has been extended. An extensive analysis of the overall error characteristics was carried out theoretically and the results were confirmed experimentally. The instrument is capable of measuring the mean square value of periodic waveform to within 2%. Normal distribution noise of standard deviation between 1V and 3V can be measured with similar accuracy. The accuracy and the upper frequency limit are determined by the ' aperture time'of the sampling process. The errors arising in the sampling instrument depend on the number of levels used. / Thesis / Master of Engineering (MEngr)

A portable special purpose computer (s.p.c.) is described which provides decimal readouts of the first four moments of a fluctuating voltage v on four separate registers. A fifth register provides a readout of the measuring time which can be within the range 10 ms. to 30 Hrs. The s.p.c. can be switched to another mode which provides a measure of the cumulative amplitude distribution of v within sixteen positive and negative levels. Salient characteristics of the s.p.c. are as follows: (a) There are no low frequency limitations. The upper frequency limit, established by error considerations, is about 5 kHz with 99.73% confidence that the error is within 1%. (b) At the end of the measuring time T, all the four moments are immediately available in magnitude and sign. (c) The outputs can be available in any code, the only change necessary being in the code of the counting readout registers. (d) All computations for a sample are completed before the next sample arrives so that programming and unnecessary storage facilities are eliminated. The voltage input v is rectified and sampled systematically by an equi-interval a.d. converter. The samples, together with the sign bit, are fed into special purpose digital multipliers based on a "weighted feed" principle. The outputs from these multipliers, with the sign bit, arc fed to accumulators via parallel adders for each of the moments. The overflows of these accumulators are shown to be contributions to the various moments and are fed to the decimal display registers. Direct computation of the standard deviation (σ) of the input, from measured first and second moments has also been investigated. A theoretical analysis of the various errors which occur in such an s.p.c. has been made. Results indicate that for most signals the overall error is within 1% for all four moments. Finally, the development of a universal arithmetic cell, for use in iterative and near-iterative arrays, is reported in this thesis. It is shown that use of such arrays in the arithmetic units of the s.p.c. can lead to a considerably simplified design. / Thesis / Doctor of Philosophy (PhD)