No description available.

No description available.

No description available.

No description available.

No description available.

The Skynet IV satellite will provide a medium for an integrated digital communications network. This will use the packet-oriented techniques employed in many modern communications systems. One important role of the system will be to provide jam-resistant services. The advent of sophisticated electronic jammers has required the application of complex error-correcting codes and data interleaving techniques. When the satellite link forms part of a wider network, these have profound effects upon the performance of the data link protocol. This project has examined some of these effects. Terrestrial data link control protocols were found to be very inefficient, and a number of enhancements to these protocols have been proposed. An implementation of the enhanced protocols has been tested within a simulation environment. The simulator was written in Simula, an object-oriented programming language. The performance of the link was observed to be highly dependent upon the error environment presented by the underlying physical layer service (in this case a frequency-hopped spread spectrum anti-jam satellite circuit). A model of the physical layer was combined with a link layer simulator. The model used an unusual technique to reduce the computational requirements of the simulator. The project revealed that a conventional anti-jam satellite circuit is unsuitable for carriage of packetised data services. However, a number of simple changes to the protocol and error control techniques may yield a significant increase in the performance, permitting use of the service even in the harsh error environments presented by hostile jammers. These results are to be used in the specification of future satellite modems.

Thesis (Ph. D.)--University of Hawaii at Manoa, 1982. / Bibliography: leaves 188-191. / Microfiche. / xi, 191 leaves, bound ill. 29 cm

Recent designs for low-density parity-check (LDPC) codes have exhibited capacity approaching performance for large block length, overtaking the performance of turbo codes. While theoretically impressive, LDPC codes present some challenges for practical implementation. In general, LDPC codes have higher encoding complexity than turbo codes both in terms of computational latency and architecture size. Decoder circuits for LDPC codes have a high routing complexity and thus demand large amounts of circuit area. / There has been recent interest in developing analog circuit architectures suitable for decoding. These circuits offer a fast, low-power alternative to the digital approach. Analog decoders also have the potential to be significantly smaller than digital decoders. / In this thesis we present a novel and efficient approach to LDPC encoder / decoder (codec) design. We propose a new algorithm which allows the parallel decoder architecture to be reused for iterative encoding. We present a new class of LDPC codes which are iteratively encodable, exhibit good empirical performance, and provide a flexible choice of code length and rate. / Combining the analog decoding approach with this new encoding technique, we design a novel time-multiplexed LDPC codec, which switches between analog decode and digital encode modes. In order to achieve this behaviour from a single circuit we have developed mode-switching gates. These logic gates are able to switch between analog (soft) and digital (hard) computation, and represent a fundamental circuit design contribution. Mode-switching gates may also be applied to built-in self-test circuits for analog decoders. Only a small overhead in circuit area is required to transform the analog decoder into a full codec. The encode operation can be performed two orders of magnitude faster than the decode operation, making the circuit suitable for full-duplex applications. Throughput of the codec scales linearly with block size, for both encode and decode operations. The low power and small area requirements of the circuit make it an attractive option for small portable devices. / Thesis (PhDTelecommunications)--University of South Australia, 2004.

Thesis (MEng (Research))--University of South Australia, 1993

Thesis (PhD)--University of South Australia, 1996