Neste trabalho analisamos e propomos a utilização de TDM (Time Division Multiplexing) nativo canalizado/estruturado em redes PON (Passive Optical Network) com padrão GPON (Gigabit Passive Optical Network), com ênfase na estrutura de transmissão do legado das redes de telefonia. O objetivo principal é obter um aumento na eficiência de banda transmitida através da fragmentação de sinais E1 sem que seja necessário o uso de técnicas de emulação de circuito (que reduzem a eficiência de banda devido à adição de cabeçalhos). Inicialmente, é descrito o transporte TDM em redes GPON, como efetuado pelos equipamentos comerciais atuais através de duas técnicas: CES - Circuit Emulation Service e TDM nativo não estruturado. Em seguida, é introduzido o conceito de comutação digital visando sua aplicação no transporte TDM nativo estruturado em redes GPON. Nesta etapa, é proposta uma solução para este transporte, é descrito o protocolo utilizado bem como seu funcionamento. Por fim, como prova de conceito, é apresentada uma implementação em HDL (Hardware Description Language) para FPGA (Field Programmable Gate Array). / In this work we analyze and propose the use of native channeled /structured TDM (Time Division Multiplexing) in GPON (Gigabit Passive Optical Network), with emphasis on the structure for transmission of the telephone network legacy. The main target is to achieve an increase in transmitted bandwidth efficiency by fragmenting E1 signals, thus avoiding the use of circuit emulation techniques (which reduce the bandwidth efficiency due to overhead addition). Initially, it is described in TDM transport in GPON networks, as it is performed in present commercial equipment by two techniques: CES - Circuit Emulation Service and Native TDM - unstructured. Next, we introduce the concepts of digital switching aiming its application on the transport of native and structured TDM in GPON. At this stage, we propose a transport solution, describe its protocol and functionalities. Finally, for concept proof, we present an implementation in HDL (Hardware Description Language) meant to FPGA (Field Programmable Gate Array) application.

L’utilisation de réseaux de neurones artificiels pour divers types de traitements d’information bio-inspirés est une technique de plus en plus répandue dans le domaine de l’intelligence artificielle. Leur fonctionnement diffère avantageusement de celui des ordinateurs conventionnels en permettant une plus grande parallélisation des calculs, ce qui explique pourquoi autant d’efforts sont déployés afin de réaliser une plate-forme matérielle dédiée à leur simulation. Pour ce projet, une architecture matérielle flexible simulant efficacement un réseau de neurones à décharges est présentée. Celle-ci se distingue des architectures existantes notamment parce qu’elle utilise une approche de simulation à événements discrets et parce qu’elle permet une détection efficace des événements simultanés. Ces caractéristiques en font une plate-forme de choix pour la simulation de réseaux de neurones à décharges de plus de 100 000 neurones où un niveau important de synchronie des décharges neuronales est atteint. Afin d’en démontrer les performances, une application en traitement d’images utilisant cette architecture a été réalisée sur FPGA. Cette application a permis de démontrer que la structure proposée pouvait simuler jusqu’à 2[indice supérieur 17] neurones et traiter des dizaines de millions d’événements par secondes lorsque cadencé à 100 MHz.

The development of dedicated cryptography systems for applications requiring low cost and consumption has been the current focus of research. This work addresses the design and performance analysis of cryptographic algorithms AES-128 (NIST standard), PRESENT-80 and CLEFIA-128 (ISO/IEC standard for Lightweight Cryptography), im-plemented in FPGA (Basys 3 Artix-7 - 28 nm technology) using VHDL. Performance metrics were analyzed and compared: occupied area in the FPGA, throughput (Mbps), efficiency (Mbps/slice), energy efficiency (Ws/bit) and current consumption. The metrics were obtained through the synthesis and implementation tool in FPGA, Vivado Design Suites (Xilinx), and by means of a current measurement prototype, which uses the Ada-fruit INA219 sensor board (Sensor from Texas Instruments) and microcontroller Arduino Uno (Atmega328 - Atmel). We also analyzed the graphical representation of current con-sumption through the mathematical model based on the Welch periodogram, applied on the current consumption variables during the data encryption process. The results show current curves that facilitate the identification and comparison of the algorithms. The data of area consumption, processing speed and efficiency in the FPGA obtained satisfactory performance in comparison with other implementations existing in the literature, besides providing relevant information to choose an algorithm of encryption. / O desenvolvimento de sistemas dedicados de criptografia, para aplicações que exigem baixo custo e consumo tem sido enfoque atual de pesquisas. Este trabalho aborda o projeto e análise de desempenho dos algoritmos de criptografia AES-128 (padrão NIST), PRESENT-80 e CLEFIA-128 (padrão ISO/IEC para Criptografia Leve), implementados em FPGA (Basys 3 Artix-7 – tecnologia de 28 nm), utilizando VHDL. Foram analisadas e comparadas as métricas de desempenho: área ocupada no FPGA, velocidade de proces-samento (Mbps), eficiência (Mbps/slice), eficiência energética (Ws/bit) e consumo de corrente. As métricas foram obtidas através da ferramenta de síntese e implementação em FPGA, Vivado Design Suites (Xilinx), e por meio de um protótipo de medição de corrente, que utiliza a placa sensor Adafruit INA219 (sensor da Texas Instruments) e microcontro-lador Arduino Uno (Atmega328 - Atmel). Foram analisadas também a representação grá-fica do consumo de corrente através do modelo matemático baseado no periodograma de Welch, aplicado sobre as variáveis de consumo de corrente durante o processo de encrip-tação de dados. Os resultados mostram curvas de corrente que facilitam a identificação e comparação dos algoritmos. Os dados de consumo de área, velocidade processamento e eficiência no FPGA obtiveram desempenho satisfatório, em comparação com outras im-plementações existentes na literatura, além de fornecer informação relevante para escolha de um algoritmo de criptografia.

Image De-noising forms an integral part of image processing. It is used as a standalone algorithm for improving the quality of the image obtained through camera as well as a starting stage for image processing applications like face recognition, super resolution etc. Non Local Means (NL-Means) and Bilateral Filter are two computationally complex de-noising algorithms which could provide good de-noising results. Due to its computational complexity, the real time applications associated with these letters are limited. In this thesis, we propose the use of hardware accelerators such as GPU (Graphics Processing Units) and FPGA (Field Programmable Gate Arrays) to speed up the filter execution and efficiently implement using them. GPU based implementation of these letters is carried out using Open Computing Language (Open CL). The basic objective of this research is to perform high speed de-noising without compromising on the quality. Here we implement a basic NL-Means filter, a Fast NL-Means filter, and Bilateral filter using Gauss Polynomial decomposition on GPU. We also propose a modification to the existing NL-Means algorithm and Gauss Polynomial Bilateral filter. Instead of Gaussian Spatial Kernel used in standard algorithm, Box Spatial kernel is introduced to improve the speed of execution of the algorithm. This research work is a step forward towards making the real time implementation of these algorithms possible. It has been found from results that the NL-Means implementation on GPU using Open CL is about 25x faster than regular CPU based implementation for larger images (1024x1024). For Fast NL-Means, GPU based implementation is about 90x faster than CPU implementation. Even with the improved execution time, the embedded system application of the NL-Means is limited due to the power and thermal restrictions of the GPU device. In order to create a low power and faster implementation, we have implemented the algorithm on FPGA. FPGAs are reconfigurable devices and enable us to create a custom architecture for the parallel execution of the algorithm. It was found that the execution time for smaller images (256x256) is about 200x faster than CPU implementation and about 25x faster than GPU execution. Moreover the power requirements of the FPGA design of the algorithm (0.53W) is much less compared to CPU(30W) and GPU(200W).

With the emergence of Industry 4.0, there is a pronounced emphasis on the necessity for enhanced flexibility in assembly processes. In the domain of bolt-tightening, this transition is evident. Tools are now required to navigate a variety of bolts and unpredictable tightening methodologies. Each bolt, possessing distinct tightening parameters, necessitates a specific sequence to prevent issues like bolt cross-talk or unbalanced force. This thesis introduces an approach that integrates advanced computing techniques with machine learning to address these challenges in the tightening areas. The primary objective is to offer edge computation for bolt detection and tightening tools' precise localization. It is realized by leveraging visual-inertial data, all encapsulated within a System-on-Chip (SoC) Field Programmable Gate Array (FPGA). The chosen approach combines visual information and motion detection, enabling tools to quickly and precisely do the localization of the tool. All the computing is done inside the SoC FPGA. The key element for identifying different bolts is the YOLOv3-Tiny-3L model, run using the Deep-learning Processor Unit (DPU) that is implemented in the FPGA. In parallel, the thesis employs the Error-State Extended Kalman Filter (ESEKF) algorithm to fuse the visual and motion data effectively. The ESEKF is accelerated via a full implementation in Register Transfer Level (RTL) in the FPGA fabric. We examined the empirical outcomes and found that the visual-inertial localization exhibited a Root Mean Square Error (RMSE) position of 39.69 mm and a standard deviation of 9.9 mm. The precision in orientation determination yields a mean error of 4.8 degrees, offset by a standard deviation of 5.39 degrees. Notably, the entire computational process, from the initial bolt detection to its final localization, is executed in 113.1 milliseconds. This thesis articulates the feasibility of executing bolt detection and visual-inertial localization using edge computing within the SoC FPGA framework. The computation trajectory is significantly streamlined by harnessing the adaptability of programmable logic within the FPGA. This evolution signifies a step towards realizing a more adaptable and error-resistant bolt-tightening procedure in industrial areas. / Med framväxten av Industry 4.0, finns det en uttalad betoning på nödvändigheten av ökad flexibilitet i monteringsprocesser. Inom området bultåtdragning är denna övergång tydlig. Verktyg krävs nu för att navigera i en mängd olika bultar och oförutsägbara åtdragningsmetoder. Varje bult, som har distinkta åtdragningsparametrar, kräver en specifik sekvens för att förhindra problem som bultöverhörning eller obalanserad kraft. Detta examensarbete introducerar ett tillvägagångssätt som integrerar avancerade datortekniker med maskininlärning för att hantera dessa utmaningar i skärpningsområdena. Det primära målet är att erbjuda kantberäkning för bultdetektering och åtdragningsverktygs exakta lokalisering. Det realiseras genom att utnyttja visuella tröghetsdata, allt inkapslat i en System-on-Chip (SoC) Field Programmable Gate Array (FPGA). Det valda tillvägagångssättet kombinerar visuell information och rörelsedetektering, vilket gör det möjligt för verktyg att snabbt och exakt lokalisera verktyget. All beräkning sker inuti SoC FPGA. Nyckelelementet för att identifiera olika bultar är YOLOv3-Tiny-3L-modellen, som körs med hjälp av Deep-learning Processor Unit (DPU) som är implementerad i FPGA. Parallellt använder avhandlingen algoritmen Error-State Extended Kalman Filter (ESEKF) för att effektivt sammansmälta visuella data och rörelsedata. ESEKF accelereras via en fullständig implementering i Register Transfer Level (RTL) i FPGA-strukturen. Vi undersökte de empiriska resultaten och fann att den visuella tröghetslokaliseringen uppvisade en Root Mean Square Error (RMSE) position på 39,69 mm och en standardavvikelse på 9,9 mm. Precisionen i orienteringsbestämningen ger ett medelfel på 4,8 grader, kompenserat av en standardavvikelse på 5,39 grader. Noterbart är att hela beräkningsprocessen, från den första bultdetekteringen till dess slutliga lokalisering, exekveras på 113,1 millisekunder. Denna avhandling artikulerar möjligheten att utföra bultdetektering och visuell tröghetslokalisering med hjälp av kantberäkning inom SoC FPGA-ramverket. Beräkningsbanan är avsevärt effektiviserad genom att utnyttja anpassningsförmågan hos programmerbar logik inom FPGA. Denna utveckling innebär ett steg mot att förverkliga en mer anpassningsbar och felbeständig skruvdragningsprocedur i industriområden.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / This paper describes a 300 Mega Bit Per Second (MBPS) Front End Processor (FEP) prototype completed in early 1993. The FEP implements a patent pending parallel frame synchronizer (frame sync) design in 12 Actel 1240 Field Programmable Gate Arrays (FPGA's). The FEP also provides (255,223) Reed-Solomon (RS) decoding and a High Performance Parallel Interface (HIPPI) output interface. The recent introduction of large RAM based FPGA's allows greater high speed data processing integration and flexibility to be achieved. A proposed FEP implementation based on Altera 10K50 FPGA's is described. This design can be implemented on a single slot 6U VME module, and includes a PCI Mezzanine Card (PMC) for a commercial Fibre Channel or Asynchronous Transfer Mode (ATM) output interface module. Concepts for implementation of (255,223) RS and Landsat 7 Bose-Chaudhuri-Hocquenghem (BCH) decoding in FPGA's are also presented. The paper concludes with a summary of the advantages of high speed data processing in FPGA's over Application Specific Integrated Circuit (ASIC) based approaches. Other potential data processing applications are also discussed.

Fixed Broadband Wireless Access (FBWA) is a technology aimed at providing high-speed wireless Internet access, over a wide area, from devices such as personal computers and laptops. FBWA channels are defined in the range of 1-20 MHz which makes the RF front end (RFE) design extremely challenging. In its pursuit to standardize the Broadband Wireless Access (BWA) technologies, IEEE working group 802.16 for Broadband Wireless Access has released the fixed BWA standard IEEE 802.16 – 2004 in 2004. This standard is further backed by a consortium, of leading wireless vendors, chip manufacturers and service providers, officially known as Wireless Interoperability for Microwave Access (WiMAX). In general, any wireless base station (BS), supporting a number of contiguous Frequency Division Multiplexed (FDM) channels has to incorporate an RF front end (RFE) for each RF channel. The precise job of the RFE is to filter the desired channel from a group of RF channels, digitize it and present it to the subsequent baseband system at the proper sampling rate. The system essentially has a bandpass filter (BPF) tuned to the channel of interest followed by a multiplier which brings the channel to a suitable intermediate frequency (IF). The IF output is digitized by an ADC and then brought to the baseband by an appropriate digital multiplier. The baseband samples, thus generated, are at the ADC sampling rate which is significantly higher than the target sampling rate, which is defined by the wireless protocol in use. As a result a sampling rate conversion (SRC) is performed on these baseband samples to bring the channel back to the target sampling rate. Since the input sampling rate need not be an integer multiple of the target sampling rate, Fractional SRC (FSRC) is required in most of the cases. Instead of using a separate ADC and IF section for each individual channels, most systems use a common IF section, followed by a wideband ADC, which operates over a wide frequency band containing a group of contiguous FDM channels. In this case a channelizer is employed to digitally extract the individual channels from the digital IF samples. We formally call this system a receiver channelizer. Such an implementation presents considerable challenge in terms of the computational requirement and of course the cost of the BS. The computational complexity further goes up for FBWA system where channel bandwidth is in the order of several MHz. Though such a system has been analyzed for narrow band wireless systems like GSM, to the best of our knowledge no analysis seems to have been carried out for a wideband system such as WiMAX. In this work, we focus on design of a receiver channelizer for WiMAX BS, which can simultaneously extract a group of contiguous FDM RF channels supported by the BS. The main goal is to obtain a simple, low cost channelizer architecture, which can be implemented in an FPGA. There are a number of techniques available in the literature, from Direct Digital Conversion to Polyphase FFT Filter Banks (PFFB), which can do the job of channelization. But each of them operates with certain constraints and, as a result, suits best to a particular application. Further all of these techniques are generic in nature, in the sense that their structure is independent of any particular standard. With regard to computational requirement of these techniques, PFFB is the best, with respect to the number of complex multiplications required for its implementation. But it needs two very stringent conditions to be satisfied, viz. the number of channels to be extracted is equal to the decimation factor and the sampling rate is a power of 2 times baseband bandwidth. Clearly these conditions may not be satisfied by different wireless communication standards, and in fact, this is not satisfied by the WiMAX standard. This gives us the motivation to analyze the receiver channelizer for WiMAX BS and to find an efficient and low cost architecture of the same. We demonstrate that even though the conditions required by PFFB are not satisfied by the WiMAX standard, we can modify the overall architecture to include the PFFB structure. This is achieved by dividing the receiver channelizer into two blocks. The first block uses the PFFB structure to separate the desired number of channels from the input samples. This process also achieves an integer SRC by a factor that is equal to the number of channels being extracted. This block generates baseband outputs whose sampling rates are related to their target sampling rate by a fractional multiplication factor. In order to bring the channels to their target sampling rate, each output from the PFFB block is fed to a FSRC block, whose job is to use an efficient FSRC algorithm to generate the samples at the target sampling rate. We show that the computational complexity, as compared to the direct implementation, is reduced by a factor, which is approximately equal to the square of the number of channels. After mathematically formulating the receiver channelizer for WiMAX BS, we perform the simulation of the system using a software tool. There are two basic motives behind the simulation of the system which has a mathematical model. Firstly, the software simulation will give an idea whether the designed system is physically realizable. Secondly, this will help in designing the logic for different blocks of the system. Once these individual blocks are simulated and tested, they can be smoothly ported onto an FPGA. For simulation purpose, we parameterize the receiver channelizer in such a way that it can be reconfigured for different ADC sampling rates and IF frequencies, by changing the input clock rate. The system is also reconfigurable in terms of the supported channel bandwidth. This is achieved by storing all the filter coefficients pertaining to each channel type, and loading the required coefficients into the computational engine. Using this methodology we simulate the system for three different IF frequencies (and the corresponding ADC sampling rates) and three different channel types, thus leading to nine different system configurations. The simulation results are in agreement with the mathematical model of the system. Further, we also discuss some important implementation issues for the reconfigurable receiver channelizer. We estimate the memory requirement for implementing the system in an FPGA. The implementation delay is estimated in terms of number of samples. The thesis is organized in five chapters. Chapter 1 gives a brief introduction about the WiMAX system and different existing channelization architecture followed by the outline of the proposed receiver channelizer. In chapter 2, we analyze the proposed receiver channelizer for WiMAX BS and evaluate its computational requirements. Chapter 3 outlines the procedure to generate the WiMAX test signal and specification of the all the filters used in the system. It also lists the simulation parameters and records the results of the simulation. Chapter 4 presents the details of a possible FPGA implementation. We present the concluding remarks and future research directions in the final chapter.

After a brief review of machine learning techniques and applications, this Ph.D. thesis examines several approaches for implementing machine learning architectures and algorithms into hardware within our laboratory. From this interdisciplinary background support, we have motivations for novel approaches that we intend to follow as an objective of innovative hardware implementations of dynamically self-reconfigurable logic for enhanced self-adaptive, self-(re)organizing and eventually self-assembling machine learning systems, while developing this new particular area of research. And after reviewing some relevant background of robotic control methods followed by most recent advanced cognitive controllers, this Ph.D. thesis suggests that amongst many well-known ways of designing operational technologies, the design methodologies of those leading-edge high-tech devices such as cognitive chips that may well lead to intelligent machines exhibiting conscious phenomena should crucially be restricted to extremely well defined constraints. Roboticists also need those as specifications to help decide upfront on otherwise infinitely free hardware/software design details. In addition and most importantly, we propose these specifications as methodological guidelines tightly related to ethics and the nowadays well-identified workings of the human body and of its psyche.

This master thesis is focused on the theoretical description and practical implementation of software defined transmitter. The main aim of this thesis was made the prototype of software defined transmitter in FM band. Theoretical part is determined to description of basic parts of equipment and working principles to understand the basic principle of digital transmitters and define the appropriate component base for construction. Discussed are used types of A/D and D/A converters, blocks of digital signal processing and the roles, which these components performs. The second part is focused practical. Specified are suitable types of components and block diagram is proposed for following electrical connection and printed circuit board in Eagle program as a plug-in modul for developmental platform Arduino. The main point is program, which sets and controls the transmitter. Next important part is impedance match and antenna tuning, which is explain in practical part of thesis. The result is prototype of software defined transmitter compatible with Arduino Uno platform.

<div>Electrical nerve stimulation (ENS) is an emerging therapy for many neurological disorders. Compared with conventional one-way stimulations, closed-loop ENS approaches increase the stimulation efficacy and minimize patient's discomfort by constantly adjusting the stimulation parameters according to the feedback biomarkers from patients. Wireless neurostimulation devices capable of both stimulation and telemetry of recorded physiological signals are welcome for closed-loop ENS systems to improve the quality and reduce the costs of treatments, and real-time digital signal processing (DSP) engines processing and extracting features from recorded signals can reduce the data transmission rate and the resulting power consumption of wireless devices. Electrically-evoked compound action potential (ECAP) is an objective measure of nerve activity and has been used as the feedback biomarker in closed-loop ENS systems including neural response telemetry (NRT) systems and a newly proposed autonomous nerve control (ANC) platform. It's desirable to design a DSP engine for real-time processing of ECAP in closed-loop ENS systems. </div><div><br></div><div>This thesis focuses on developing the DSP architecture for real-time processing of ECAP, including stimulus artifact rejection (SAR), denoising, and extraction of nerve fiber responses as biomedical features, and its VLSI implementation for optimal hardware costs. The first part presents the DSP architecture for real-time SAR and denoising of ECAP in NRT systems. A bidirectional-filtered coherent averaging (BFCA) method is proposed, which enables the configurable linear-phase filter to be realized hardware efficiently for distortion-free filtering of ECAPs and can be easily combined with the alternating-polarity (AP) stimulation method for SAR. Design techniques including folded-IIR filter and division-free averaging are incorporated to reduce the computation cost. The second part presents the fiber-response extraction engine (FREE), a dedicated DSP engine for nerve activation control in the ANC platform. FREE employs the DSP architecture of the BFCA method combined with the AP stimulation, and the architecture of computationally efficient peak detection and classification algorithms for fiber response extraction from ECAP. FREE is mapped onto a custom-made and battery-powered wearable wireless device incorporating a low-power FPGA, a Bluetooth transceiver, a stimulation and recording analog front-end and a power-management unit. In comparison with previous software-based signal processing, FREE not only reduces the data rate of wireless devices but also improves the precision of fiber response classification in noisy environments, which contributes to the construction of high-accuracy nerve activation profile in the ANC platform. An application-specific integrated circuit (ASIC) version of FREE is implemented in 180-nm CMOS technology, with total chip area and core power consumption of 19.98 mm² and 1.95 mW, respectively. </div><div><br></div>