Thesis (Ph. D.)--Lehigh University, 2000. / Includes vita. Includes bibliographical references (leaves 145-151).

Discrete charge-trapping flash memories are more promising than their floating-gate counterparts due to their physically discrete-trapping and coupling-free nature. Si3N4 is conventional material as charge-trapping layer (CTL) for charge storage. The shortcomings of Si3N4 are its low dielectric constant and small barrier height at its interface with SiO2 tunneling layer. Therefore, this research aims to investigate new materials as CTL for improving the performance of the memory devices. The charge-trapping characteristics of La2O3 with and without nitrogen incorporation were investigated. Compared with the memory device with La2O3 as CTL, the one with nitrided La2O3 (LaON) showed larger memory window, higher program/erase (P/E) speeds and smaller charge loss, due to the nitrided La2O3 film exhibiting less crystallized structure, higher trap density induced by nitrogen incorporation, and suppressed leakage by nitrogen passivation. In order to further improve the performance of the memory device with LaON CTL, a device with band-engineered LaTiON/LaON structure as CTL was also explored, and demonstrated to have better performance than the one with LaON CTL. This was ascribed to the variable tunneling path of charge carriers under P/E and retention modes (realized by the band-engineered charge-trapping layer), high trap density of LaTiON, and large barrier height at the LaTiON/SiO interface. SrTiO 3and BaTiO3 ,both ofwhich are typical perovskite-type dielectrics, also possess distinguished characteristics as CTL, including remarkably high dielectric constant and large conduction-band offset relative to SiO2. The charge-trapping properties of SrTiO3 with and without fluorine incorporation were studied. The device with fluorinated SrTiO3 film showed promising performance in terms of higher P/E speeds at a low gate voltage, better endurance and data retention compared with that without fluorine treatment. These advantages were associated with generated deep-level traps, reduced leakage path, and enhanced strength of the film due to the highest electro-negativity of the fluorine atoms incorporated in the film. The charge-trapping properties of BaTiO3 with and without Zr incorporation were also investigated, where Zr incorporated in BaTiO3 could strengthen the dielectric film and improve its thermodynamic stability. The device with Zr incorporation exhibited similar memory window as the one without Zr incorporation, but higher program speed at low gate voltage, better endurance and data retention, due to the Zr-doped BaTiO3 exhibiting higher charge-trapping efficiency and higher density of traps with deeper energy levels. Besides nitride-based memories, nanocrystal-based memories are another type of charge-trapping memories, where nanocrystals (NCs) embedded into a dielectric are used for charge storage. Memory devices with Ga2O3 NCs as CTL were investigated, which are compatible with the CMOS process. The Ga2O3 NCs displayed higher trap density than the Ga2O3 dielectric film. Moreover, compared with the device with Ga2O 3NCs as CTL, the one with nitrided Ga2O3 NCs showed larger memory window, higher operating speed and better data retention, mainly due to higher charge-trapping efficiency of the nitrided Ga2O3 NCs and nitrogen-induced suppressed formation of interlayer at the Ga2O/SiO interface. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Discrete charge-trapping flash memory is being developed for the next-generation commercial flash-memory applications due to its advantages over the traditional floating-gate counterpart. Currently, Si3N4 is widely used as charge-trapping layer (CTL). However, Si3N4 has low dielectric constant and small conduction-band offset with respect to the SiO2 tunneling layer, imposing limitation on further applications. Therefore, this research emphasized on investigating new dielectrics with appropriate fabrication methods to replace Si3N4 as CTL for achieving improved memory performance. Firstly, GeON CTL annealed at different temperatures was investigated. The memory device with post-deposition annealing at 600 0C exhibited the largest memory window, the best charge retention performance, and the highest reliability. These good results are due to the fact that optimal annealing temperature could suppress shallow traps and also produce new traps with desirable energy levels in the CTL. Since ZnON has a negative conduction-band offset (NCBO) with respect to Si, the traps located in the bandgap of ZnON should have deep energy levels. The memory performances of ZrON film with and without Zn doping were studied. Experimental results showed that ZrZnON film had higher program speed and better charge retention performance due to many deeper trap levels induced by the Zn doping, as well as higher erase speed due to the direct recombination of electrons at these deeper trap levels with incoming holes and the intermediary role of these deeper trap levels under erase mode. MoO3 is another NCBO dielectric with a high K value and many oxygen vacancies. La2O3, a rare-earth metal oxide, is a promising dielectric as CTL. To combine the advantages of both La2O3 and MoO3, Mo-doped La2O3 was proposed as a new CTL. Compared to the device with pure La2O3, the one with LaMoO film as CTL had significantly larger C-V hysteresis window, much higher P/E speeds, and better charge retention due to the deeper-level traps and deeper quantum wells created by the LaMoO film. Nitrogen incorporation is a popular approach to increase the trap density in the bulk of CTL. In this research, the memory performances of GdTiO films with and without nitrogen incorporation were compared. Since the nitrogen incorporation induced smaller equivalent oxide thickness, produced nitride-related traps with desirable energy level and larger cross-section for charge capture, the GdTiON film possessed better memory performance than the GdTiO film. Finally, fluorine plasma was employed to improve the quality of blocking layer. The memory device with AlOF blocking layer obtained higher program speed, better reliability and better charge retention than that based on AlO blocking layer. The improved performance was due to the fact that the fluorine incorporation passivated the defects and removed the excess oxygen in the bulk of the blocking layer. In summary, dielectric plays important roles in the performance of charge-trapping flash memory. Memory devices with GeON, ZrZnON, LaMoO, or GdTiON as charge trapping layer and AlOF as blocking layer can produce large memory window, high program/erase speed and good charge retention. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Non-volatile memories are an emerging storage technology with wide applica- tions in many important areas. This study focuses on new storage techniques for flash memories and phase-change memories. Flash memories are currently the most widely used type of non-volatile memory, and phase-change memories (PCMs) are the most promising candidate for the next-generation non-volatile memories. Like magnetic recording and optical recording, flash memories and PCMs have their own distinct properties, which introduce very interesting data storage problems. They include error correction, cell programming and other coding problems that affect the reliability and efficiency of data storage. Solutions to these problems can signifi- cantly improve the longevity and performance of the storage systems based on flash memories and PCMs. In this work, we study several new techniques for data storage in flash memories and PCMs. First, we study new types of error-correcting codes for flash memories – called error scrubbing codes –that correct errors by only increasing cell levels. Error scrubbing codes can correct errors without the costly block erasure operations, and we show how they can outperform conventional error-correcting codes. Next, we study the programming strategies for flash memory cells, and present an adaptive algorithm that optimizes the expected precision of cell programming. We then study data storage in PCMs, where thermal interference is a major challenge for data reliability. We present two new coding techniques that reduce thermal interference, and study their storage capacities and code constructions.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 97-112). Available also in a digital version from Dissertation Abstracts.

As semiconductor device scaling is reaching the 45 nm node, the need for novel device concept, architecture and new materials has never been so pressing as today. Flash memories, the driving force of semiconductor memory market in recent years, also face the same or maybe more severe challenges to meet the demands for high-density, low-cost, low-power, high-speed, better endurance and longer retention time. As traditional continuous floating gate flash struggles to balance the trade-off between high speed and retention requirement, nanocrystal (NC) floating gate flash has attracted more and more interest recently due to its advantages over traditional flash memories in many areas such as better device scaling, lower power consumption and improved charge retention. However, there are still two major challenges remaining for embedded NC synthesis: the deposition method and the size and distribution control. Nowadays using bio-nano techniques such as DNA, virus or protein for NC synthesis and assembly has become a hot topic and feasible for actual electronic device fabrication. In this dissertation a new method for NC deposition wherein a colloidal suspension of commercially-available NCs was organized using a self-assembled chaperonin array. The chaperonin array was applied as a scaffold to mediate NCs into an assembly with uniform spatial distribution on Si wafers. By using this method, we demonstrated that colloidal PbSe and Co NCs in suspension can self-assemble into ordered arrays with a high density of up to 10¹²cm⁻². MOSCAP and MOSFET memory devices were successfully fabricated with the chaperonin protein mediated NCs, showing promising memory functions such as a large charge storage capacity, long retention time and good endurance. The charge storage capacity with respect to material work function, NC size and density was explored. In addition to NC engineering, the tunnel barrier was engineered by replacing traditional SiO₂ by high-k material HfO₂, giving a higher write/erase speed with a reduced effective oxide thickness (EOT). Suggestions for future research in this direction are presented in the last part of this work. / text

Mainstream non-volatile memory technology dominated by the planar Flash transistor with continuous floating-gate has been historically improved in density and performance primarily by means of process scaling, but is currently faced with significant hindrances to its future scaling due to fundamental constraints of electrostatics and reliability. This dissertation is based on exploring two pathways for circumventing scaling limitations of the state-of-the-art Flash memory technology. The first part of the dissertation is based on demonstrating a vertical Flash memory transistor with nanocrystal floating-gate, while the second part is based on developing fundamental understanding of the operation of Phase Change Memory. A vertical Flash transistor can allow the theoretical minimum cell area and a nanocrystal floating-gate on the sidewalls is shown to allow a thinner gate-stack further conducive to scaling while still providing good reliability. Subsequently, the application of a technique of protein-mediated assembly of preformed nanocrystals to the sidewalls of the vertical Flash transistor is also demonstrated and characterized. This technique of ordering pre-formed nanocrystals is beneficial towards achieving reproducible nanocrystal size uniformity and ordering especially in a highly scaled vertical Flash cell, rendering it more amenable to scaling and manufacturability. In both forms, the vertical Flash memory cell is shown to have good electrical characteristics and reliability for the viability of this cell design and implementation. In the remaining part of this dissertation, studies are undertaken towards developing fundamental understanding of the operational characteristics of Phase Change Memory (PCM) technology that is expected to replace floating-gate Flash technology based on its potential for scaling. First, a phenomenon of improving figures of merit of the PCM cell with operational cycles is electrically characterized. Based on the electrical characterization and published material characterization data, a physical model of an evolving "active region" of the cell is proposed to explain the improvement of the cell parameters with operational cycles. Then, basic understanding is developed on early and erratic retention failure in a statistically significant number of cells in a large array and, electrical characterization and physical modeling is used to explain the mechanism behind the early retention failure.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2009. / Includes bibliographical references (p. 47-50).

Thesis (M.S.)--Tennessee Technological University, 2009. / Title from title page screen (viewed on June 29, 2010). Bibliography: leaves 51-56.