The cable television (CATV) industry has grown significantly since its inception in the late 1940’s. Originally, a CATV network was comprised of several homes that were connected to community antennae via a network of coaxial cables. The only signal processing done was by an analogue amplifier, and transmission only occurred in one direction (i.e. from the antennae/head-end to the subscribers). However, as CATV grew in popularity, demand for services such as pay-per-view television increased, which lead to supporting transmission in the upstream direction (i.e. from subscriber to the head-end). This greatly increased the signal processing to include frequency diplexers. CATV service providers began to expand the bandwidth of their networks in the late 90’s by switching from analogue to digital technology. In an effort to regulate the manufacturing of new digital equipment and ensure interoperability of products from different manufacturers, several cable service providers formed a non-for-profit consortium to develop a data-over-cable service interface specification (DOCSIS). The consortium, which is named CableLabs, released the first DOCSIS standard in 1997. The DOCSIS standard has been upgraded over the years to keep up with increased consumer demand for large bandwidths and faster transmission speeds, particularly in the upstream direction. The latest version of the DOCSIS standard, DOCSIS 3.1, utilizes orthogonal frequency-division multiple access (OFDMA) technology to provide upstream transmission speeds of up to 1 Gbps. As cable service providers begin the process of upgrading their upstream receivers to comply with the new DOCSIS 3.1 standard, they require a means of testing the various functions that an upstream receiver may employ. It is convenient for service providers to employ cable modem (CM) plus channel emulator to perform these tests in-house during the product development stage. Constructing the emulator in digital technology is an attractive option for testing. This thesis approaches digital emulation by developing a digital model of the CMs and upstream channel in a DOCSIS 3.1 network. The first step in building the emulator is to simulate its operations in MATLAB, specifically upstream transmission over the network. The MATLAB model is capable of simulating transmission from multiple CMs, each of which transmits using a specific “transmission mode.” The three transmission modes described in the DOCSIS 3.1 standard are included in the model. These modes are “traffic mode,” which is used during regular data transmission; “fine ranging mode,” which is used to perform fine timing and power offset corrections; and “probing” mode, which is presumably used for estimating the frequency response of the channel, but also is used to further correct the timing and power offsets. The MATLAB model is also capable of simulating the channel impairments a signal may encounter when traversing the upstream channel. Impairments that are specific to individual CMs include integer and fractional timing offsets, micro-reflections, carrier phase offset (CPO), fractional carrier frequency offset (CFO), and network gain/attenuation. Impairments common to all CMs include carrier hum modulation, AM/FM ingress noise, and additive white Gaussian noise (AWGN). It is the hope that the MATLAB scripts that make up the simulation be translated to Verilog HDL to implement the emulator on a field-programmable gate array (FPGA) in the near future. In the event that an FPGA implementation is pursued, research was conducted into designing efficient fractional delay filters (FDFs), which are essential in the simulation of micro-reflections. After performing an FPGA implementation cost analysis between various FDF designs, it was determined that a Kaiser-windowed sinc function FDF with roll-off parameter β = 3.88 was the most cost-efficient choice, requiring at total of 24 multipliers when implemented using an optimized structure.

The demand for efficient and reliable high rate communication is ever increasing. In this thesis we study different challenges in such systems, and their possible solutions. A goal for many years has been to implement as much as possible of a radio system in the digital domain, the ultimate goal being so called software defined radio (SDR) where the inner workings of a radio standard can be changed completely by changing the software. One important part of an SDR receiver is the high speed analog-to-digital converter (ADC) and one path to reach this high speed is to use a number of parallel, time-interleaved, ADCs. Such ADCs are, however, sensitive to sampling instant offsets, DC level offsets and gain offsets. This thesis discusses estimators based on fractional-delay filters and one application of these estimmators is to estimate and calibrate the relative delay, gain, and DC level offset between the ADCs comprising the time interleaved ADC. In this thesis we also present a technique for carrier frequency offset (CFO) estimation in orthogonal frequency division multiplexing (OFDM) systems. OFDM has gone from a promising digital radio transmission technique to become a mainstream technique used in several current and future standards. The main attractive property of OFDM is that it is inherently resilient to multipath reflections because of its long symbol time. However, this comes at the cost of a relatively high sensitivity to CFO. The proposed estimator is based on locating the spectral minimas within so-called null or virtual subcarriers embedded in the spectrum.~The spectral minimas are found iteratively over a number of symbols and is therefore mainly useful for frequency offset tracking or in systems where an estimate is not immediately required, such as in TV or radio broadcasting systems. However, complexity-wise the estimator is relatively easy to implement and it does not need any extra redundancy beside a nonmodulated subcarrier. The estimator performance is studied both in a channel with additive white Gaussian noise and in a multipath frequency selective channel environment. Interpolators and decimators are an important part of many systems, e.g. radio systems, audio systems etc. Such interpolation (decimation) is often performed using cascaded interpolators (decimators) to reduce the speed requirements in different parts of the system. In a fixed-point implementation, scaling is needed to maximize the use of the available word lengths and to prevent overflow. In the final part of the thesis, we present a method for scaling of multistage interpolators/decimators using multirate signal processing techniques. We also present a technique to estimate the output roundoff noise caused by the internal quantization.