This master thesis report covers an investigation of how FPGA based hardware can be used to create customizable measurement instruments, for test of electrical equipment in JAS 39 Gripen. The investigation is done at Saab Support and Services in Arboga. Electrical equipment are gradually replacing functions, which previously have been obtained by other systems, in safety critical environments. Since the functions are safety critical, they require regular testing in order to verify proper operation. The aircraft JAS 39 Gripen, which is manufactured and developed by Saab, is an example of such system. Proper operation of the avionics in it are essential in order to maintain flying safety. There already exist systems today that can verify the functionality of electronics in JAS 39 Gripen. However, there are a number of scenarios where those test systems are somewhat inflexible. More flexible test systems are often desired. This flexibility can be obtained by using congurable hardware, suggestively with FPGAs. This approach is investigated in this master thesis.

In this thesis, a direct digital synthesis (DDS) based function generator design module is presented, defined and implemented using two digital hardware modeling/design languages namely SystemC and VHDL. The simulation, synthesis and applicability performances of these two design languages are compared by following all digital hardware design stages. The advantages and open issues of SystemC based hardware design flow are emphasized in order to be a reference for future studies. SystemC initially appeared as a modeling language like HDL design languages. In the last years, SystemC gained popularity also as a hardware design language and it is expected to become alternative to traditional design languages. Using a single platform for hardware modeling, design and verification reduces the spent time and cost. The designed DDS function generator module supports standard I2C and UART communication protocols and it is in ready to use format for digital applications. In this thesis, the function generator module VHDL code is implemented into Xilinx FPGA and verified on the hardware platforms.

The aim of the project is to design a concept of function generator with digital synthesis. The device will be controlled using microprocessor which allows synthesizing basic functions (sin, square, raw) as well as arbitrary functions stored in memory. User friendly graphical interface will be controlled by keyboard and rotary switch (IRC). The work emphasizes correct selection of DDS clock source, circuit elements and proper application of signal filtration method with attention to low distortion and low output phase noise.