En esta tesis hemos identificado tres de los mayores cuellos de botella para el rendimiento y escalabilidad de las arquitecturas many-core CMP de memoria compartida. En particular, los mecanismos de sincronización de barrera y cerrojo cuando presentan alta contención, así como los protocolos hardware de coherencia de caché en el mantenimiento de la coherencia del uso de bloques memoria compartidos en una jerarquía de memoria. Para paliar estas deficiencias y aprovechar más el rendimiento de estas arquitecturas, hemos propuesto tres mecanismos hardware: GBarrier, para un mecanismo de barreras eficiente; GLock, para un manejo justo y eficiente de la contención en el acceso a las secciones críticas protegidas por cerrojos; y ECONO, un protocolo de coherencia muy simple que aporta gran eficiencia a bajo costo. La tesis concluye que nuestras propuestas resuelven de manera eficiente los problemas de rendimiento derivados de implementaciones ineficientes para sincronización y coherencia en arquitecturas many-core CMP. / In this thesis we have identified three of the major problems that restrict efficiency and scalability in future shared-memory tiled many-core CMPs. In particular, the synchronization operations of barriers and locks under highly-contended scenarios, and the hardware-based cache coherence protocols when dealing with the maintenance of coherence of all memory blocks across all levels of a memory hierarchy. To alleviate such performance bottlenecks in order to harness the computational power of such systems, we have proposed three hardware-based mechanisms: GBarrier, a very efficient barrier mechanism; GLock, an efficient and fair mechanism to implement highly-contended locks; and ECONO, a simple and efficient hardware coherence protocol. In light of our performance results obtained in this thesis, we can affirm that our proposals represent a step forward towards the resolution of the challenges that many-core CMP architectures will pose to computer architects.

The increasing number of cores every generation poses challenges for high-performance in-memory database systems. While these systems use sophisticated high-level algorithms to partition a query or run multiple queries in parallel, they also utilize low-level synchronization mechanisms to synchronize access to internal database data structures. Developers often spend significant development and verification effort to improve concurrency in the presence of such synchronization. The Intel ® Transactional Synchronization Extensions (Intel ® TSX) in the 4th Generation Core™ Processors enable hardware to dynamically determine whether threads actually need to synchronize even in the presence of conservatively used synchronization. This paper evaluates the effectiveness of such hardware support in a commercial database. We focus on two index implementations: a B+Tree Index and the Delta Storage Index used in the SAP HANA ® database system. We demonstrate that such support can improve performance of database data structures such as index trees and presents a compelling opportunity for the development of simpler, scalable, and easy-to-verify algorithms.