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The compressive behavior of an annular rubber seal constrained in a pipe and the interaction between the pipe and the seal was studied experimentally using a specially designed test fixture that allowed the concentric alignment of the seal within the pipe and its axial compression using an electro-hydraulic Instron load frame. The hoop strain introduced in the pipe wall, due to the constraint of lateral expansion of the seal, displayed a parabolic distribution with a maximum value at the mid-height of the seal similar to the parabolic shape of the lateral expansion of the seal. The magnitude of the pipe strain increased with the friction coefficient of the interface between the seal and the compression rings, strain rate, and shape factor for a constant gap between the seal and the pipe wall. The relationship between the apparent compressive modulus and the shape factor (beyond experimental range) was studied using FEA. / October 2016

Abstract This paper presents a new four-dimensional (4-D) smooth quadratic autonomous chaotic system, which can present periodic orbit, chaos, and hyperchaos under the conditions on different parameters. Importantly, the system can generate a four-wing hyper-chaotic attractor and a pair of coexistent doublewing hyper-chaotic attractors with two symmetrical initial conditions. Furthermore, a four-wing transient chaos occurs in the system. The dynamic analysis approach- in the paper involves time series, phase portraits, Poincaré maps, bifurcation diagrams, and Lyapunov exponents, to investigate some basic dynamical behaviors of the proposed 4-D system.

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Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal.

The purpose of this thesis is to develop methods to generate minimum-energy consumption trajectories for a point-to-point motion under pre-defined kinematic and dynamic constraints for robotic manipulators. With respect to other trajectory optimization methods, the work presented in this thesis provides two new methods to the scientific literature. The proposed methods improve the handling of the constraints in trajectory optimization methods as well as reducing the computational complexity of redundant/hyper-redundant manipulator systems.

As a result of the microprocessor system research and the development of VLSI manufacturing process technology, the recent trend and development in high performance computer have toward to multi-core architecture. However current multi-core architectures are designed by the symmetric multi processors (SMP) concept. In traditional SMP mechanism, there are only data link between processor cores. So a single thread only can be handled by a single core, it limits the usage rate in multi-core and performance can not increase. This paper proposed a scalable chip multiprocessor architecture, which is called Hyper-scalar. The Principal characteristic of the architecture is ¡§design the interconnect control mechanisms for instructions in the multi-core¡¨. Some single scalar processor cores in Hyper-scalar architecture can be dynamically grouped as an n-way superscalar accelerator to improve the instruction-level parallelism, which is called accelerator group. Hyper-scalar combines the advantages of superscalar and multithreaded architecture; Hence, this architecture can not only enhance single-threaded performance by using accelerate group but also supports multithreaded applications. The paper based on ARM instruction set, to analyze how to create the interactive control mechanisms for instruction in the multi-core, and how to enhance the performance of a single thread in the Hyper-scalar architecture. It can be divided into four parts: register flow, memory flow, instruction control flow, chop of multi cycle instruction. When instructions are issued into the processor, they must be attached dependence tags that can solve the dependence between all issued instructions. All instructions can exchange the data through the virtual shared register file (VSRF) mechanism, and all instructions are executed only when the operands are available. In the memory flow part: we solve the dependence problem with a simple technique¡Xto execute instruction in instruction order. In instruction control flow part: in order to improve performance, we perform speculation execution mechanism, so the instructions can out of order execution beyond the basic block. Finally because there are some multi cycle instructions in the ARM instruction set, in hyper-scalar framework can chop into many one cycle instructions to further enhance performance. The simulation Model is written by SystemC, a modeling language based on C++ is to provide hardware-oriented simulation platform and the MediaBench suite is selected for the experiments. On average, the Hyper-scalar architecture can accelerate single-threaded performance by 50% to 300% using 2 ~ 8 cores.

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal