Recent years have witnessed an increasing number of mobile devices such as smartphones and tablets characterized by low computing and storage capabilities. Meanwhile, there is an explosive growth of applications on mobile devices that require high computing and storage capabilities. These challenges lead to the introduction of cloud computing empowering mobile devices with remote computing and storage resources. However, cloud computing is centrally designed, thus encountering noticeable issues such as high communication latency and potential vulnerability. To tackle these problems posed by central cloud computing, Mobile Edge Cloud (MEC) has been recently introduced to bring the computing and storage resources in proximity to mobile devices, such as at base stations or shopping centers. Therefore, MEC has become a key enabling technology for various emerging use cases such as autonomous driving and tactile internet. Despite such a potential benefit, the design of MEC is challenging for the deployment of applications. First, as MEC aims to bring computation and storage resources closer to mobile devices, MEC servers that provide those resources become incredibly diverse in the network. Moreover, MEC servers typically have a small footprint design to flexibly place at various locations, thus providing limited resources. The challenge is to deploy applications in a cost-efficient manner. Second, applications have stringent requirements such as high mobility or low latency. The challenge is to deploy applications in MEC to satisfy their needs. Considering the above challenges, this thesis aims to study the orchestration of MEC applications. In particular, for computation offloading, we propose offloading schemes for immersive applications in MEC such as Augmented Reality or Virtual Reality (AR/VR) by employing application characteristics. For resource optimization, since many MEC applications such as gaming and streaming applications require the support of network functions such as encoder and decoder, we first present placement schemes that allow efficiently sharing network functions between multiple MEC applications. We then introduce the design of the proposed MANO framework in MEC, advocating the joint orchestration between MEC applications and network functions. For mobility support, low latency applications for use cases such as autonomous driving have to seamlessly migrate from one MEC server to another MEC server following the mobility of mobile device, to guarantee low latency communication. Traditional migration approaches based on virtual machine (VM) or container migration attempt to suspend the application at one MEC server and then recover it at another MEC server. These approaches require the transfer of the entire VM or container state and consequently lead to service interruption due to high migration time. Therefore, we advocate migration techniques that takes advantage of application states.

Nuclear spectroscopy is an interdisciplinary subject of physics and electronics, which adopts state-of-the-art digital electronic technology and computer technology to analyze the information in ionizing radiation. The use of FPGAs shortens the development cycles of the digital circuit design and reduces system noise with compact electronics size. As a result, digital spectrometers with FPGAs are gaining popularity in research and industrial markets. The motivation behind this work was to replace conventional analog electronics with modern digital technology to provide an excellent energy resolution for different kinds of nuclear detectors and experiments. In this thesis, a SiPM-based scintillation detector is first designed based on the basic principles of ionizing radiation. The readout circuit of the detector is given in detail. Subsequently, a real-time DPP module is designed using the FPGA of Lattice. The system noise of the DPP is measured, compared, and analyzed after the hardware verification and implementation of digital algorithms to assess the capability of the DPP module. Afterward, digital pulse processing algorithms are investigated in detail to improve the performance of the designed digital module. The design and implementation of multipass moving average and trapezoidal filter are presented. The PZC and BLR are designed and implemented according to the analysis of the trapezoidal filter’s weakness to have a better energy resolution of the digital system. Algorithms are designed and implemented on a Simulink platform. Experimental results and analyses are provided at the end of this thesis. The acquired data are analyzed in real-time or by offline software. Spectra and resolutions are demonstrated of different detectors to evaluate the performance of digital module and algorithms implementation. The resolution of the scintillation detector can be obtained to 4.2%, which is almost the optimal value based on their datasheet. The implementations of digital algorithms are verified. Other applications are provided, such as coincidence and cosmic muons measurements.

As semiconductor technologies develop, a System-on-Chip (SoC) that integrates all semiconductor intellectual property (IP) cores is suggested and widely used for various applications. A traditional bus interconnection does not support transmitting data between IP cores for high performance. Because of this reason, a Network-on-Chip (NoC) has been suggested to provide an efficient and scalable solution to interconnect among all IP cores. High throughput and low latency have recently become the main important factors of NoC for achieving hard guaranteed real-time systems. In order to guarantee these factors and provide real-time service (i.e., Guaranteed Service, GS), the circuit switching (CS) approach has been widely utilized. The CS approach allocates mutually exclusive paths to transmitting data between different sources and destinations using dedicated NoC resources. However, the exclusive occupancy of the allocated path reduces the efficiency of the overall use of NoC resources. In order to solve this problem, Space-Division-Multiplexing (SDM) and Time-Division-Multiplexing (TDM) techniques have been suggested. SDM implements a circuit switching technique by assigning physically different NoC-links between different connections. Path connections of the SDM technique based on spatial resources assignment do not provide high scalability. In contrast to this, using virtual time slots for a path connection, the TDM technique can share physical links between exclusively established connections, thereby improving NoC path diversity. For all of these mentioned techniques, the factor that significantly impacts the system efficiency or performance scaling is how the path is allocated. In recent years, a dynamic connection allocation approach that can cope with highly dynamic workloads has been gaining attention due to the sudden and diverse demands of applications in real-time systems. There are two groups in the dynamic connection allocation approach. One is a distributed allocation technique, and the other is a centralized allocation technique. While distributed allocation exploits additional logic integrated into the NoC-routers for path search and allocation, the centralized approach makes use of a central unit to manage the path allocation problem. There are several algorithms for the centralized allocation technique. Trellis search-based allocation approach shows the best performance among them. Many algorithms related to centralized connection allocators have been studied extensively during the past decade. However, relatively little attention was paid to methodology in analyzing and evaluating the centralized connection allocation algorithms. In order to further develop the algorithms, it is necessary to understand and evaluate the centralized connection allocator by establishing a new analysis methodology. Thus, this thesis presents a performance analysis methodology for the trellis search-based allocation approach. Firstly, this thesis proposes a system model for analysis. Secondly, performance metrics are defined. Finally, the analysis results of each performance metric related to the trellis search-based allocation approach are presented. Through this analysis, the performance of the trellis search-based allocation approach can be accurately analyzed. Although a simulation is not performed, the upper limit of performance of the trellis search-based allocation approach can also be predicted through the analysis metrics. Additionally, we introduce the general formulation of the trellis search-based path allocation algorithm. The weight values among available paths through the branch metric and path metric are proposed to enable higher performance path connection. Furthermore, according to network size, topology, TDM, interface load delivery, and router internal storage, the performance of trellis search-based path allocation algorithms is also described. In the end, the Application Specific Instruction Processor (ASIP) hardware platform customized for the trellis search-based path allocation algorithm is presented. The shortest available and lowest-cost (SALC) path search algorithm is proposed to improve the success rate of path connection in the ASIP hardware platform. We evaluate the algorithm performance and implementation synthesis results. In order to realize the dynamic connection approach, a short execution cycle of ASIP time is essential. We develop several algorithms to achieve this short execution cycle. The first one is a rectangular region of search algorithm that allows adapting the size and form of path search region according to the particular source-destination positions and considers actual operational constraints. The average execution cycles for searching an optimum path are decreased because the unnecessary region for path-search is excluded. The second one is a path-spreading search algorithm that separates between involved routers and uninvolved routers in path search. The involved routers are selected and spread out from source to destination at each intermediate trellis-search process. The path-search overhead is considerably reduced due to the router involvements. The third one is a three-directional path-spreading search algorithm that eliminates one direction movement among four spreading movements. Because of this reason, the trellis search-based path connection algorithm, which omits the back-tracing process, can be implemented in the ASIP platform. Thus, the whole algorithm execution time can be halved. The last one is a moving regional path search algorithm that significantly reduces computation complexity by selecting a constant dimensional path-search region that affects performance and moving the region from source to destination. The moving regional path search algorithm achieves a considerable decrement of computational complexity.:1 Introduction 1 1.1 NoC-interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Connection allocation in a Network-on-Chip 7 2.1 Circuit Switching NoCs . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Guaranteed Service in NoCs . . . . . . . . . . . . . . . . . . . 7 2.1.2 Spatial-Division-Multiplexing technique . . . . . . . . . . . . 8 2.1.3 Time-Division-Multiplexing technique . . . . . . . . . . . . . 10 2.2 System architectures employing circuit switching NoCs . . . . . . . . 11 2.2.1 Static and dynamic connection allocation . . . . . . . . . . . 12 2.2.2 Distributed connection allocation technique . . . . . . . . . . 14 2.2.3 Centralized connection allocation technique . . . . . . . . . . 16 2.2.4 Algorithms for centralized connection allocation . . . . . . . . 17 2.2.4.1 Software based run-time path allocation approach . 18 2.2.4.2 Trellis search-based allocation approach . . . . . . . 19 3 Performance analysis methodology for a centralized connection allocator 23 3.1 System model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 Performance metrics and analysis methodology . . . . . . . . . . . . 25 3.3 System simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4 Trellis search-based path allocation algorithm 45 4.1 General formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.1 Trellis graph structure . . . . . . . . . . . . . . . . . . . . . . 45 4.1.2 Survivor path selection criterion . . . . . . . . . . . . . . . . . 52 ix 4.1.2.1 Branch metric and path metric . . . . . . . . . . . . 52 4.1.2.2 The shortest-available and lowest-cost path selection criterion . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2 Algorithm Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.1 Network topology . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.2 Network size . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2.3 Time-Division-Multiplexing . . . . . . . . . . . . . . . . . . . 61 4.2.4 NoC interface load diversity . . . . . . . . . . . . . . . . . . . 63 4.2.5 The internal storage of the router . . . . . . . . . . . . . . . . 66 5 ASIP approach for Trellis search-based connection allocation 73 5.1 System model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.1.1 Trellis search-based ASIP platform architecture . . . . . . . . 74 5.2 Algorithm for improving success rates of path connection . . . . . . . 81 5.2.1 SALC algorithm for Trellis search-based ASIP platform . . . . 81 5.2.2 Performance evaluation of the SALC algorithm . . . . . . . . 88 5.2.2.1 Simulation results . . . . . . . . . . . . . . . . . . . 88 5.2.2.2 Synthesis results . . . . . . . . . . . . . . . . . . . . 91 5.3 Algorithm for reducing path-search time . . . . . . . . . . . . . . . . 93 5.3.1 Rectangular regional path search algorithm . . . . . . . . . . 93 5.3.2 Path-spreading search algorithm . . . . . . . . . . . . . . . . 99 5.3.3 Three directional path-spreading search algorithm . . . . . . 108 5.3.4 Moving regional path search algorithm . . . . . . . . . . . . . 114 5.3.5 Performance evaluation . . . . . . . . . . . . . . . . . . . . . 123 5.3.5.1 Simulation results . . . . . . . . . . . . . . . . . . . 123 5.3.5.2 Synthesis results . . . . . . . . . . . . . . . . . . . . 126 6 Conclusion and Future work 131 6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Bibliography 135

Communication systems are experiencing a fundamental change. There are novel applications that require an increased performance not only of throughput but also latency, reliability, security, and heterogeneity support from these systems. To fulfil the requirements, future systems understand communication not only as the transport of bits but also as their storage, processing, and relation. In these systems, every network node has transport storage and computing resources that the network operator and its users can exploit through virtualisation and softwarisation of the resources. It is within this context that this work presents its results. We proposed distributed coded approaches to improve communication systems. Our results improve the reliability and latency performance of the transport of information. They also increase the reliability, flexibility, and throughput of storage applications. Furthermore, based on the lessons that coded approaches improve the transport and storage performance of communication systems, we propose a distributed coded approach for the computing of novel in-network applications such as the steering and control of cyber-physical systems. Our proposed approach can increase the reliability and latency performance of distributed in-network computing in the presence of errors, erasures, and attackers.

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XLI

Massenanpassung, kleine Losgrößen, hohe Variabilität der Produkttypen und ein sich während des Lebenszyklus einer industriellen Anlage änderndes Produktportfolio sind aktuelle Trends der Industrie. Durch eine zunehmende Entkopplung der Entwicklung von Software- und Hardwarekomponenten im industriellen Kontext, entstehen immer häufiger Kompatibilitätsprobleme innerhalb von industriellen Steuerungen. In dieser Arbeit wird mittels Literaturrecherche und angewandter Forschung ein Strategiekonzept zur Kompatibilitätsprüfung hergeleitet und diskutiert. Dieses vierphasige Konzept ermittelt Inkompatibilitäten zwischen Software- und Hardwarekomponenten im Umfeld von industriellen Steuerungen und ermöglicht Testingenieuren das frühzeitige Erkennen von Problemen. Durch eine automatische Durchführung der Kompatibilitätsprüfung auf einem externen Industrie PC kann die Kompatibilitätsprüfung sowohl beim Aufspielen neuer Software auf die industrielle Steuerung als auch beim Neustart der Steuerung ablaufen. Somit werden Änderungen an den Komponenten stetig erkannt und Inkompatibilitäten vermieden. Weiterhin kann durch die frühzeitige Erkennung sichergestellt werden, dass eine Anlage dauerhaft lauffähig bleibt. Anhand einer Diskussion werden Mittel festgestellt, um die Robustheit und Anwendbarkeit des vorgestellten Konzeptes zusätzlich zu festigen.:1 Motivation 1 1.1 Aufgabenanalyse 3 1.1.1 Forschungsfragen und Teilaufgaben 3 1.1.2 Aufgabenkomplexe 4 1.1.3 Eingrenzung der Aufgabenstellung 5 1.1.4 Ziel der Arbeit 6 1.1.5 Festsetzung von Formulierungen 6 2 Einführung und Stand der Technik 7 2.1 VIBN von industriellen Anlagen 7 2.1.1 Teststrategien aus der VIBN 9 2.1.1.1 Model-in-the-Loop 9 2.1.1.2 Software-in-the-Loop 9 2.1.1.3 Hardware-in-the-Loop 10 2.1.1.4 Konklusion und Forschungsbestrebungen 11 2.2 CS in industriellen Anlagen 12 2.2.1 Sicherheitsziel 13 2.2.2 Teststrategien aus der CS 13 2.2.2.1 Signaturbasierte Erkennung 14 2.2.2.2 Anomaliebasierte Erkennung 14 2.2.2.3 Konklusion und Forschungsbestrebungen 16 2.3 Interoperabilität als Kompatibilitätsmaß 16 2.4 Testautomatisierung und Test Case Generierung 17 2.5 Allgemeine Softwareteststrategien 17 2.5.1 Modellbasiertes Testen 17 2.5.2 Funktionale Tests 18 2.6 Allgemeine Hardware Teststrategien 19 2.6.1 Modellbasiertes Testen 19 2.6.2 Manuelles Testen 19 2.7 Interoperabilität in industriellen Anlagen 20 2.7.1 Definitionen der Interoperabilität 20 2.7.2 Herausforderungen der Interoperabilität 22 2.7.3 Implementierung von Interoperabilität 22 2.7.3.1 Syntaktische Interoperabilität 23 2.7.3.2 Semantische Interoperabilität 23 2.7.4 Vertikale Integration 24 2.7.5 Horizontale Integration 25 3 Anforderungsanalyse 27 3.1 Adaption von Strategien der VIBN und CS 27 3.2 Anforderungen 28 3.2.1 Anforderungen an die Kompatibilitätsprüfung 28 3.2.2 Anforderungen an die Hardwarekomponenten 29 3.2.3 Anforderungen an die Softwarekomponenten 29 4 Konzept 30 4.1 Komponenten des Teststrategiekonzeptes 30 4.1.1 SPS Selbsttest 32 4.1.2 Export & Import des Soll-Zustandes 32 4.1.3 Ermittlung des Ist-Zustandes 35 4.1.4 Vergleich des Soll- & Ist-Zustandes 35 4.2 Fehlerdetektionstabellen 36 4.3 Reaktionen auf Inkompatibilitäten 38 5 Evaluation 39 5.1 Methodik und Evaluationskriterien 39 5.2 Anwendungsbeispiel 39 5.3 Referenzsystem für Evaluation 41 5.4 Durchführung Evaluation 41 5.5 Erfüllung der Anforderungen an die Kompatibilitätsprüfung 46 6 Diskussion 48 6.1 Beantwortung der Forschungsfragen 48 6.2 Diskussion zur Forschungsmethodik 48 6.3 Bewertung des Konzeptes 49 7 Zusammenfassung und Ausblick 50 7.1 Zusammenfassung 50 7.2 Ausblick und weitere Forschungsarbeit 51 Literaturverzeichnis 52 / Mass customization, small batch sizes, high variability of product types and a changing product portfolio during the life cycle of an industrial plant are current trends in the industry. Due to an increasing decoupling of the development of software and hardware components in an industrial context, compatibility problems within industrial control systems arise more and more frequently. In this thesis, a strategy concept for compatibility testing is derived and discussed by means of literature review and applied research. This 4-phased strategy concept identifies incompatibilities between software and hardware components in the industrial control environment and enables test engineers to detect problems at an early stage. By automating the compatibility test on an external I-PC, the test can be run both when new software is installed on the industrial controller and when the controller is restarted. Thus, changes to the components are constantly detected and incompatibilities are avoided. Furthermore, early incompatibility detection can ensure that a system remains permanently operational. Based on a discussion, additionally strategies are identified to consolidate the robustness and applicability of the presented concept.:1 Motivation 1 1.1 Aufgabenanalyse 3 1.1.1 Forschungsfragen und Teilaufgaben 3 1.1.2 Aufgabenkomplexe 4 1.1.3 Eingrenzung der Aufgabenstellung 5 1.1.4 Ziel der Arbeit 6 1.1.5 Festsetzung von Formulierungen 6 2 Einführung und Stand der Technik 7 2.1 VIBN von industriellen Anlagen 7 2.1.1 Teststrategien aus der VIBN 9 2.1.1.1 Model-in-the-Loop 9 2.1.1.2 Software-in-the-Loop 9 2.1.1.3 Hardware-in-the-Loop 10 2.1.1.4 Konklusion und Forschungsbestrebungen 11 2.2 CS in industriellen Anlagen 12 2.2.1 Sicherheitsziel 13 2.2.2 Teststrategien aus der CS 13 2.2.2.1 Signaturbasierte Erkennung 14 2.2.2.2 Anomaliebasierte Erkennung 14 2.2.2.3 Konklusion und Forschungsbestrebungen 16 2.3 Interoperabilität als Kompatibilitätsmaß 16 2.4 Testautomatisierung und Test Case Generierung 17 2.5 Allgemeine Softwareteststrategien 17 2.5.1 Modellbasiertes Testen 17 2.5.2 Funktionale Tests 18 2.6 Allgemeine Hardware Teststrategien 19 2.6.1 Modellbasiertes Testen 19 2.6.2 Manuelles Testen 19 2.7 Interoperabilität in industriellen Anlagen 20 2.7.1 Definitionen der Interoperabilität 20 2.7.2 Herausforderungen der Interoperabilität 22 2.7.3 Implementierung von Interoperabilität 22 2.7.3.1 Syntaktische Interoperabilität 23 2.7.3.2 Semantische Interoperabilität 23 2.7.4 Vertikale Integration 24 2.7.5 Horizontale Integration 25 3 Anforderungsanalyse 27 3.1 Adaption von Strategien der VIBN und CS 27 3.2 Anforderungen 28 3.2.1 Anforderungen an die Kompatibilitätsprüfung 28 3.2.2 Anforderungen an die Hardwarekomponenten 29 3.2.3 Anforderungen an die Softwarekomponenten 29 4 Konzept 30 4.1 Komponenten des Teststrategiekonzeptes 30 4.1.1 SPS Selbsttest 32 4.1.2 Export & Import des Soll-Zustandes 32 4.1.3 Ermittlung des Ist-Zustandes 35 4.1.4 Vergleich des Soll- & Ist-Zustandes 35 4.2 Fehlerdetektionstabellen 36 4.3 Reaktionen auf Inkompatibilitäten 38 5 Evaluation 39 5.1 Methodik und Evaluationskriterien 39 5.2 Anwendungsbeispiel 39 5.3 Referenzsystem für Evaluation 41 5.4 Durchführung Evaluation 41 5.5 Erfüllung der Anforderungen an die Kompatibilitätsprüfung 46 6 Diskussion 48 6.1 Beantwortung der Forschungsfragen 48 6.2 Diskussion zur Forschungsmethodik 48 6.3 Bewertung des Konzeptes 49 7 Zusammenfassung und Ausblick 50 7.1 Zusammenfassung 50 7.2 Ausblick und weitere Forschungsarbeit 51 Literaturverzeichnis 52

The scope of this work is the development of a 60 GHz flexible transceiver frontend by adopting an economic prototyping approach. Such a platform can validate the proposed protocols for the 60 GHz band in a real wireless environment, especially the physical layer security concept. The development course uses the hybrid architecture with off-the-shelf components and custom-designed RF chain blocks on printed circuit technology. Challenge in this approach is the coarse resolution of the selected manufacturing technology and higher process tolerance. This work extends the state-of-the-art by proposing etching-resilient RF chain blocks on wide bandwidths. It presents the design validation of each block and performance analysis for various manufacturing conditions. The study also reviews and proposes a high-frequency interconnect model for bondwires, vital in a frontend design. Parasitics' compensation of the interconnects at millimeter-wave operation is proposed, compatible with printed circuit technology. The 60 GHz frontend is realized by packaging the designed RF blocks and off-the-shelf components with optimized and characterized high-frequency interconnects. The frontend, equipped with a tailor-made antenna duplexer, is reconfigurable for frequency, power, and modulation scheme. The developed frontend is characterized for local oscillator, transmitter, and receiver operations. The adaptability of the frontend allows it to be used as an agent in a heterogeneous network. Two units of the developed frontends are used in a network for frequency domain channel sounding. The antenna duplexer ensures channel reciprocity in bidirectional sounding campaigns. Matched two-way channel response is achieved in various indoor environments, which endorses the frontend for channel reciprocity key generation. Finally, the frontend units are successfully deployed in a physical layer security demonstrator.:Abstract Chapter1: Introduction Chapter 2: Fundamentals and state-of-the-art Chapter 3: The design Chapter 4: Integration and characterization Chapter 5: Application example: Channel sounder Chapter 6: Summary and future work Appendices Bibliography

Microbatteries are being considered as the critical components for portable and smart microelectronics, including remote sensors, micro-electromechanical systems, microrobots, implantable medical devices, and the Internet of Things, owing to their high energy densities, long life span, and facile on-chip integration. To date, tremendous efforts have been devoted to developing new methodologies for building high-performance microbatteries with minimum footprint areas. However, an effective and reliable fabrication procedure that is compatible with the modern microelectronics industry has not yet been reported for microbatteries so far. Two main issues need to be considered for the device design: (1) pursuing satisfying energy and power densities at limited footprint area is highly desired by constructing the 3D microelectrode architecture with high aspect ratio while reducing its footprint; (2) a novel technology is highly demanded to produce the 3D microstructure following an on-chip processing route which is compatible with the manufacturing procedure of microelectronic devices. Rolled-up nanotechnology can transform a large-area planar precursor into a micrometer-sized Swiss-roll by careful strain-engineering and state-of-the-art micro-patterning techniques with a micro-origami self-assembly process, which reduces the device size for monolithic integration. This dissertation demonstrates brand-new 3D Swiss-roll microbatteries with high performance at a sub-square millimeter-scale by employing rolled-up nanotechnology. Two types of micro-batteries with different configurations have been designed and fabricated, including twin Swiss-roll and single Swiss-roll structures. The twin Swiss-roll microbattery is fabricated based on two separated Swiss-roll micro-scaffolds with a parallel structure and controllable distance between them. The tuneable mesostructure benefits the mass loading of electroactive materials, rendering the excellent energy density at a greatly reduced footprint area. The twin Swiss-roll configuration is conducive to compatibility with novel battery chemistries due to its separated parallel Swiss-roll structure. In order to further decrease the overall footprint area, a single Swiss-roll configuration is designed for a fully integrated Swiss-roll microbattery. Micro-anode and micro-cathode are integrated into a single Swiss-roll configuration with an extremely small footprint area, which benefits the integration and miniaturization of microelectronics. Finally, an integrated device composed of a single Swiss-roll microbattery and UV photodetector is successfully fabricated within 1 mm2. The concept presented here enables the high-performance microbattery that can break through the limitation on microbattery’s footprint area, which opens up the new vision for the future on-chip microelectronics.:Table of contents Chapter 1. Introduction 1 1.1. Background and motivation of this work 1 1.2. Dissertation structure 2 Chapter 2. Overview of 3D microbatteries 5 2.1. Electrochemical energy storage 5 2.2. Rechargeable zinc batteries 6 2.2.1. Alkaline rechargeable zinc batteries 7 2.2.2. Aqueous zinc ion batteries 8 2.2.3. Dual-ion hybrid zinc batteries 9 2.3. Configurations for 3D microbatteries 10 2.3.1. 3D sandwiched architecture 12 2.3.2. 3D interdigital architecture 13 2.3.3. Rolled-up microtubular architecture 15 2.4. Conclusion 17 Chapter 3. Overview of rolled-up technology 21 3.1. Self-rolled-up inorganic layers 21 3.2. Self-rolled-up polymeric shapeable platform 24 3.3. Applications of rolled-up nanomembranes for energy storage devices 26 3.3.1. Rolled-up active materials for LIBs 26 3.3.2. Rolled-up micro-platform for in-situ investigation 27 3.3.3. Rolled-up integratable 3D micro-capacitors/supercapacitors 29 Chapter 4. Experimental methods 35 4.1. Fabrication technologies 35 4.1.1. Photolithography 36 4.1.2. Electron beam evaporation 37 4.1.3. Magnetron sputtering deposition 38 4.1.4. Electrochemical deposition 39 4.2. Characterization methods 40 4.2.1. Scanning electron microscopy, focused ion beam milling, and energy dispersive spectrometry 40 4.2.2. X-ray diffraction 41 4.2.3. Raman spectroscopy 41 4.2.4. Electrochemical characterization 42 4.2.5. Finite element method simulations 43 Chapter 5. A twin Swiss-roll microbattery 45 5.1. Introduction 45 5.2. Fabrication and characterization of twin Swiss-roll microbattery 46 5.2.1. Reshape a 2D precursor to a 3D mesostructured Swiss-roll 46 5.2.2. The construction of Swiss-roll microelectrodes 48 5.3. Results and discussion 51 5.3.1. The encapsulation of twin Swiss-roll microbattery 51 5.3.2. Electrochemical performance of twin Swiss-roll microbattery 52 5.3.3. Practical applications of twin Swiss-roll microbattery 55 5.4. Conclusion 57 Chapter 6. A single Swiss-roll microbattery 59 6.1. Introduction 59 6.2. Fabrication of Swiss-roll Zn-Ag microbattery 60 6.2.1. Fabrication of micro-origami layer stack 61 6.2.2. Fabrication of battery components 63 6.2.3. Self-roll-up of single Swiss-roll microbattery 63 6.3. Results and discussion 65 6.3.1. Materials characterization 65 6.3.2. Electrolyte optimization 65 6.3.3. Electrochemical performance of single Swiss-roll microbattery 70 6.4. Conclusion 73 Chapter 7. Summary and outlook 75 7.1. Summary 75 7.2. Outlook 77 Bibliography 79 List of figures 87 List of tables 91 Versicherung 93 Acknowledgment 95 Publications and presentations 97 Curriculum vita 99

Diese Arbeit beschäftigt sich der Modulation und Regelung von Mehrpunktstromrichtern zum Antrieb elektrischer Maschinen unter Nutzung optimierter Pulsmuster. Ziel der Arbeit ist es, das Potential und die Grenzen der Modulation mit optimierten Pulsmustern unter der Randbedingung der heute vorhandenen Softwareframeworks und Rechentechnik aufzuzeigen. Darüber hinaus soll dem Leser ein gesamtheitlicher Überblick über die optimierten Pulsmuster vermittelt werden. Ausgehend vom Stand der Technik der verbreiteten Arten der Modulation werden die optimierten Pulsmuster eingeführt. Für die notwendige Berechnung der Pulsmuster als Lösung einer Optimierungsaufgabe wird ein allgemeines Konzept der mathematischen Beschreibung vorgestellt. Darauf basierend werden zehn heute verfügbare numerische Löser auf ihre Konvergenz bezüglich der Lösung des gestellten Problems untersucht. Die Ergebnisse zeigen, dass es möglich ist, optimierte Pulsmuster mit Frequenzverhältnissen mf ≤ 21 online zu berechnen und dass geeignete Löser auch bei mf ≫ 50 sicher konvergieren. Eine Analyse der gefundenen Lösungen zeigt, dass der von trägerbasierten Modulationen bekannte lineare Zusammenhang zwischen mittlerer Schaltfrequenz und Schaltverlusten bei den optimierten Pulsmustern nicht gegeben ist. Darauf aufbauend wird ein neuer Algorithmus zur Wahl verlustminimierter Pulsmuster erarbeitet. Es zeigt sich, dass dessen Einsatz auch bei mf ≫ 21 gegenüber der Raumzeigermodulation zu einer signifikanten Reduktion der Schaltverluste (ca. 20%) führt. Mit den Grundlagen der Berechnung und der Analyse der Eigenschaften der optimierten Pulsmuster, wird basierend auf dem Stand der Technik ein neuartiger lastunabhängiger Modulator entwickelt. Dieser kompensiert die Unstetigkeiten der Pulsmusterwechsel durch Regelung des Integrals des harmonischen Inhalts der Pulsmuster. Aufbauend auf diesem neuartigen Modulator wird eine parameterrobuste Maschinenregelung entworfen. Diese weist eine Dead-Beat-Dynamik der Regelung des elektrischen Momentes einer angeschlossenen Maschine auf und ermöglicht im stationären Zustand, im Gegensatz zu den bestehenden Konzepten, die Ausgabe eines unveränderten Pulsmusters. Damit wird die angestrebte minimierte Stromwelligkeit erreicht. Im letzten Teil der Arbeit wird der Einfluss einer Modulation mit optimierten Pulsmustern auf den Symmetrierungsvorgang eines selbstgeführten Dreipunkt-UStromrichter (3L-NPC-VSC) untersucht. Dabei wird eine neue Methode der Reduktion der dynamischen Zwischenkreiswelligkeit, sowie eine neuartige, in allen Arbeitspunkten stabile, Methode der statischen Zwischenkreissymmetrierung präsentiert. Alle erarbeiteten Algorithmen wurden mit Hilfe von Simulationen und Experimenten verifiziert.:1 Einleitung 1 1.1 Inhalt und Motivation der vorliegenden Arbeit 2 1.2 Experimenteller Versuchsstand 4 1.3 Verwendete Grundlagen und Kennwerte 6 1.3.1 Fourieranalyse 6 1.3.2 Laplace-Transformation 7 1.3.3 Gütekriterien 8 2 Modulation 9 2.1 Klassifikation der Generierung der Pulsmuster 9 2.2 Modulationsverfahren 11 2.2.1 Trägerbasierte Pulsweitenmodulation 11 2.2.2 Raumzeigermodulation 22 2.2.3 Optimierte Pulsmuster 25 3 Optimierte Pulsmuster 29 3.1 Optimierungskriterien 30 3.1.1 Gewichtetes Gesamt-Oberschwingungsverhältnis 30 3.1.2 Gesamt-Oberschwingungsverhältnis 30 3.1.3 Minimale Drehmomentwelligkeit 31 3.1.4 Individuelle Wichtung der Harmonischen 32 3.1.5 Verlustminimierung in der Last 33 3.1.6 Schaltverlustminimierung der Halbleiter des Umrichters 34 3.2 Formulierung der Optimierungsaufgabe der optimierten Pulsmuster 35 3.2.1 Berechnung der Fourierkoeffizienten 36 3.2.2 Notwendige Nebenbedingungen der Optimierung 38 3.3 Vergleich von Algorithmen der nichtlinearen Optimierung 38 3.3.1 Vergleich verschiedener Lösungsmethoden 39 3.3.2 Definition des für den Vergleich genutzten Problems 43 3.3.3 Dauer der Berechnung der lokalen Minima 44 3.3.4 Vergleich der lokalen Minima der verschiedenen Löser 45 3.3.5 Berechnung verlustminimaler optimierter Pulsmuster 46 3.3.6 Untersuchungen zur Auswahl der lokalen Minima 47 3.3.7 Vergleich der optimierten Pulsmuster mit SVM und CB-Modulation 56 4 Stand der Technik der Regelung von Drehstrommaschinen 60 4.1 Grundlagen der Modellierung der Asynchronmaschine 60 4.2 Klassische Ansätze der Regelung elektrischer Maschinen 62 4.2.1 Feldorientierte Regelung 62 4.2.2 Direkte Selbstregelung 69 4.2.3 Direkte Momentenregelung 72 4.2.4 Vergleich der vorgestellten klassischen Regelungsarten 75 4.3 Regelung mit optimierten Pulsmustern auf Basis der Feldorientierung 76 4.3.1 Dynamischer Modulationsfehler durch unstetige Pulsmuster 76 4.3.2 Direkte Pulsmustermodifikation 80 4.3.3 Behandlung des dynamischen Modulationsfehlers 84 4.4 Geschlossener Regelkreis 86 4.5 Regelung mit optimierten Pulsmustern auf Basis der DSC 92 4.5.1 Eigenschaften der vorgestellten Pulserzeugungsarten 94 4.5.2 Dynamischen Eigenschaften der vorgestellten Regelungsstrukturen 95 5 Verallgemeinerte Konzepte zur Nutzung optimierter Pulsmuster 98 5.1 Implementierung eines allgemeingültigen OPP-Modulators 98 5.2 Behandlung des harmonischen Anteils der Pulsmuster 104 5.3 Modulation und Modifikation der Pulsmuster bei hohem mf 105 5.4 Dead-Beat-Control auf Basis der Pulsmustermodifikation 108 5.5 Maschinen-Beobachter 109 5.5.1 Beobachter der Asynchronmaschine 111 5.5.2 Beobachter der permanenterregten Synchronmaschine 114 5.6 Geschlossener Statorflussregelkreis 115 5.6.1 Untersuchung der Sensitivität des Modells 119 5.7 Entwurf der übergeordneten Regelkreise 123 5.7.1 Entwurf des Rotorflussreglers 125 5.7.2 Entwurf des Drehzahlreglers 126 5.7.3 Begrenzung des Statorstromes 127 5.7.4 Simulative und experimentelle Ergebnisse 127 6 Zwischenkreissymmetrierung des 3L-NPC-VSC bei OPP-Modulation 135 6.1 Der Neutralpunktstrom 135 6.2 Minimierung der Neutralpunktstromwelligkeit 138 6.3 Aktive Symmetrierung 140 6.4 Integration der Regelung der Zwischenkreissymmetrie 154 7 Zusammenfassung 158 Literatur 161 Abkürzungsverzeichnis 177 Symbolverzeichnis 178 / This thesis deals with the modulation and control of multilevel converters as electrical drives using an optimized pulse pattern (OPP) modulation scheme. The aim of the work is to determine the potential and the limits of the modulation using OPPs, considering state-of-the-art software frameworks und computing technology. Furthermore the reader shell get a holistic overview of all aspects regarding the use of OPPs. Starting with the state-of-the-art of the most popular modulation schemes and their characteristics the optimized pulse patterns are introduced. A general mathematical formulation, which describes the OPP calculation as minimization problem, is shown. With this formulation, ten implementations of nonlinear constraint minimization algorithms are analyzed with regard to the convergence behavior. It is shown, that OPP can be calculated online for frequency ratios mf ≫ 21. Further, some algorithms converge reliable also for mf ≫ 50. Afterwards, the solutions of the minimization of the weighted total harmonic distortion (WTHD) problem are analyzed. It is shown, that the linear relationship between the averaged switching frequency and the switching loss, which is known from carrier based modulation schemes, does not apply for OPPs. A new method to find loss optimized pulse patterns is proposed. With this method the modulation using OPPs can reduce the converter switching losses in comparison to space vector modulation significantly (20%) also for mf ≫ 21. Based on the analysis of the found OPP solutions a novel modulator, which is independent of the parameters of the load, is proposed. This modulator compensates the discontinuities due to the pulse pattern changes by controlling the integral of the harmonic content of the modulator output. Based on this modulator a new parameter robust machine control was developed. This concept shows a dead-beat-dynamic of the control of the electrical torque and uses in contrast to state-of-the-art concepts the unmodified OPP in steady state, which leads to a minimal load current ripple. The last part of the thesis deals with the influence of using an OPP modulation on the DC-link balancing of a Three-Level Neutral-Point-Clamped Voltage-Source-Converter (3L-NPC-VSC). A new method to reduce the dynamic neutral-pointpotential-ripple as well as a new stable static balancing method are proposed. All proposed algorithms and methods are verified by simulation and experiment.:1 Einleitung 1 1.1 Inhalt und Motivation der vorliegenden Arbeit 2 1.2 Experimenteller Versuchsstand 4 1.3 Verwendete Grundlagen und Kennwerte 6 1.3.1 Fourieranalyse 6 1.3.2 Laplace-Transformation 7 1.3.3 Gütekriterien 8 2 Modulation 9 2.1 Klassifikation der Generierung der Pulsmuster 9 2.2 Modulationsverfahren 11 2.2.1 Trägerbasierte Pulsweitenmodulation 11 2.2.2 Raumzeigermodulation 22 2.2.3 Optimierte Pulsmuster 25 3 Optimierte Pulsmuster 29 3.1 Optimierungskriterien 30 3.1.1 Gewichtetes Gesamt-Oberschwingungsverhältnis 30 3.1.2 Gesamt-Oberschwingungsverhältnis 30 3.1.3 Minimale Drehmomentwelligkeit 31 3.1.4 Individuelle Wichtung der Harmonischen 32 3.1.5 Verlustminimierung in der Last 33 3.1.6 Schaltverlustminimierung der Halbleiter des Umrichters 34 3.2 Formulierung der Optimierungsaufgabe der optimierten Pulsmuster 35 3.2.1 Berechnung der Fourierkoeffizienten 36 3.2.2 Notwendige Nebenbedingungen der Optimierung 38 3.3 Vergleich von Algorithmen der nichtlinearen Optimierung 38 3.3.1 Vergleich verschiedener Lösungsmethoden 39 3.3.2 Definition des für den Vergleich genutzten Problems 43 3.3.3 Dauer der Berechnung der lokalen Minima 44 3.3.4 Vergleich der lokalen Minima der verschiedenen Löser 45 3.3.5 Berechnung verlustminimaler optimierter Pulsmuster 46 3.3.6 Untersuchungen zur Auswahl der lokalen Minima 47 3.3.7 Vergleich der optimierten Pulsmuster mit SVM und CB-Modulation 56 4 Stand der Technik der Regelung von Drehstrommaschinen 60 4.1 Grundlagen der Modellierung der Asynchronmaschine 60 4.2 Klassische Ansätze der Regelung elektrischer Maschinen 62 4.2.1 Feldorientierte Regelung 62 4.2.2 Direkte Selbstregelung 69 4.2.3 Direkte Momentenregelung 72 4.2.4 Vergleich der vorgestellten klassischen Regelungsarten 75 4.3 Regelung mit optimierten Pulsmustern auf Basis der Feldorientierung 76 4.3.1 Dynamischer Modulationsfehler durch unstetige Pulsmuster 76 4.3.2 Direkte Pulsmustermodifikation 80 4.3.3 Behandlung des dynamischen Modulationsfehlers 84 4.4 Geschlossener Regelkreis 86 4.5 Regelung mit optimierten Pulsmustern auf Basis der DSC 92 4.5.1 Eigenschaften der vorgestellten Pulserzeugungsarten 94 4.5.2 Dynamischen Eigenschaften der vorgestellten Regelungsstrukturen 95 5 Verallgemeinerte Konzepte zur Nutzung optimierter Pulsmuster 98 5.1 Implementierung eines allgemeingültigen OPP-Modulators 98 5.2 Behandlung des harmonischen Anteils der Pulsmuster 104 5.3 Modulation und Modifikation der Pulsmuster bei hohem mf 105 5.4 Dead-Beat-Control auf Basis der Pulsmustermodifikation 108 5.5 Maschinen-Beobachter 109 5.5.1 Beobachter der Asynchronmaschine 111 5.5.2 Beobachter der permanenterregten Synchronmaschine 114 5.6 Geschlossener Statorflussregelkreis 115 5.6.1 Untersuchung der Sensitivität des Modells 119 5.7 Entwurf der übergeordneten Regelkreise 123 5.7.1 Entwurf des Rotorflussreglers 125 5.7.2 Entwurf des Drehzahlreglers 126 5.7.3 Begrenzung des Statorstromes 127 5.7.4 Simulative und experimentelle Ergebnisse 127 6 Zwischenkreissymmetrierung des 3L-NPC-VSC bei OPP-Modulation 135 6.1 Der Neutralpunktstrom 135 6.2 Minimierung der Neutralpunktstromwelligkeit 138 6.3 Aktive Symmetrierung 140 6.4 Integration der Regelung der Zwischenkreissymmetrie 154 7 Zusammenfassung 158 Literatur 161 Abkürzungsverzeichnis 177 Symbolverzeichnis 178

We develop biohybrid magnetic microrobots by electrostatic self-assembly of nonmotile sperm cells and magnetic nanoparticles. Incorporating a biological entity into microrobots entails many functional advantages beyond shape templating, such as the facile uptake of chemotherapeutic agents to achieve targeted drug delivery. We present a single-step electrostatic self-assembly technique to fabricate IRONSperms, soft magnetic microswimmers that emulate the motion of motile sperm cells. Our experiments and theoretical predictions show that the swimming speed of IRONSperms exceeds 0.2 body length/s (6.8 ± 4.1 µm/s) at an actuation frequency of 8 Hz and precision angle of 45°. We demonstrate that the nanoparticle coating increases the acoustic impedance of the sperm cells and enables localization of clusters of IRONSperm using ultrasound feedback. We also confirm the biocompatibility and drug loading ability of these microrobots, and their promise as biocompatible, controllable, and detectable biohybrid tools for in vivo targeted therapy.