by Li Wai Ting. / Thesis (M.Ph.)--Chinese University of Hong Kong, 1987. / Includes bibliographical references.

Jiang, Li. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references (leaves 149-155). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts also in Chinese.

by Hu Hai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references. / Abstracts in English and Chinese. / Author's Declaration --- p.ii / Abstract --- p.iii / Acknowledgements --- p.vi / Table of Contents --- p.viii / List of Figures --- p.xi / List of Tables --- p.xiv / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Overview of This Work --- p.2 / Chapter 1.3 --- Original Contributions in the Thesis --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter Chapter 2 --- PEEC Modeling Background --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- PEEC Principles --- p.6 / Chapter 2.3 --- Meshing Scheme --- p.10 / Chapter 2.4 --- Formulae for Calculating the Partial Elements --- p.12 / Chapter 2.4.1 --- Partial Inductance --- p.12 / Chapter 2.4.2 --- Partial Capacitance --- p.14 / Chapter 2.5 --- PEEC Application Example --- p.15 / Chapter 2.6 --- Summary --- p.17 / References --- p.18 / Chapter Chapter 3 --- Mathematical Model Order Reduction --- p.20 / Chapter 3.1 --- Introduction --- p.20 / Chapter 3.2 --- Modified Nodal Analysis --- p.21 / Chapter 3.2.1 --- Standard Nodal Analysis Method Review --- p.22 / Chapter 3.2.2 --- General Theory of Modified Nodal Analysis --- p.23 / Chapter 3.2.3 --- Calculate the System Poles Using MNA --- p.27 / Chapter 3.2.4 --- Examples and Comparisons --- p.28 / Chapter 3.3 --- Krylov Subspace MOR Method --- p.30 / Chapter 3.4 --- Examples of Krylov Subspace MOR --- p.32 / Chapter 3.5 --- Summary --- p.34 / References --- p.35 / Chapter Chapter 4 --- Physical Model Order Reduction --- p.38 / Chapter 4.1 --- Introduction --- p.38 / Chapter 4.2 --- Gaussian Elimination Method --- p.39 / Chapter 4.3 --- A Lossy PEEC Circuit Model --- p.44 / Chapter 4.3.1 --- Loss with Capacitance --- p.44 / Chapter 4.3.2 --- Loss with Inductance --- p.46 / Chapter 4.4 --- Conversion of Mutual Inductive Couplings --- p.47 / Chapter 4.5 --- Model Order Reduction Schemes --- p.50 / Chapter 4.5.1 --- Taylor Expansion Based MOR Scheme (Type I) --- p.51 / Chapter 4.5.2 --- Derived Complex-valued MOR Scheme (Type II) --- p.65 / Chapter 4.6 --- Summary --- p.88 / References --- p.88 / Chapter Chapter 5 --- Concluding Remarks --- p.92 / Chapter 5.1 --- Conclusion --- p.92 / Chapter 5.2 --- Future Improvement --- p.93 / Author's Publication --- p.95

He, Xu. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references (leaves [127]-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts also in Chinese.

The adaptation of standard integrated circuit (IC) technology for biosensors in drug discovery pharmacology, neural interface systems, environmental sensors and electrophysiology requires electrodes to be electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous IC technology, complementary metal oxide semiconductor (CMOS), does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved by others. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. The scope of this work was to develop post-processing methods that meet the electrochemical and biocompatibility requirements but within the low-cost constraint. Several approaches were appraised with the two most promising designs taken forward for further investigation. Firstly, a process was developed whereby the corrodible aluminium is anodised to form nanoporous alumina and further processed to optimise its impedance. A second design included a noble metal in the alumina pores to enhance further the electrical characteristics of the electrode. Experiments demonstrated for the first time the ability to anodise CMOS metallisation to form the desired electrodes. Tests showed the electrode addressed the problems of corrosion and presented a surface that was biocompatible with the NG108-15 neuronal cell line. Difficulties in assessing the influence of alumina porosity led to the development of a novel cell adhesion assay that showed for the first time neuronal cells adhere preferentially to large pores rather than small pores or planar aluminium. It was also demonstrated that porosity can be manipulated at room temperature by modifying the anodising electrolyte with polyethylene glycol. CMOS ICs were designed as multiple electrode arrays and optimised for neuronal recordings. This utilised the design incorporating a noble metal deposited into the porous alumina. Deposition of platinum was only partially successful, with better results using gold. This provided an electrode surface suitable for electric cell-substrate impedance sensors (ECIS) and many other sensor applications. Further processing deposited platinum black to improve signal-to-noise ratio for neuronal recordings. The developed processes require no specialised semiconductor fabrication equipment and can process CMOS ICs on laboratory or factory bench tops in less than one hour. During the course of electrode development, new methods for biosensor packaging were assessed: firstly, a biocompatible polyethylene glycol mould process was developed for improved prototype assembly. Secondly, a commercial ‘partial encapsulation’ process (Quik-Pak, U.S.) was assessed for biocompatibility. Cell vitality tests showed both methods were biocompatible and therefore suitable for use in cell-based biosensors. The post-processed CMOS electrode arrays were demonstrated by successfully recording neuronal cell electrical activity (action potentials) and by ECIS with a human epithelial cell line (Caco2). It is evident that these developments may provide a missing link that can enable commercialisation of CMOS biosensors. Further work is being planned to demonstrate the technology in context for specific markets.

No description available.

The ever-increasing design complexity of modern circuits challenges our ability to verify their correctness. Therefore, various errors are more likely to escape the pre-silicon verification process and to manifest themselves after design tape-out. To address this problem, effective post-silicon validation is essential for eliminating design bugs before integrated circuit (IC) products shipped to customers. In the debug process, it becomes increasingly popular to insert design-for-debug (DfD) structures into the original design to facilitate real-time debug without intervening the circuits’ normal operation. For this so-called trace-based post-silicon validation technique, the key question is how to design such DfD circuits to achieve sufficient observability and controllability during the debug process with limited hardware overhead. However, in today’s VLSI design flow, this is unfortunately conducted in a manual fashion based on designers’ own experience, which cannot guarantee debug quality. To tackle this problem, we propose a set of automatic tracing solutions as well as innovative DfD designs in this thesis. First, we develop a novel trace signal selection technique to maximize the visibility on debugging functional design errors. To strengthen the capability for tackling these errors, we sequentially introduce a multiplexed signal tracing strategy with a trace signal grouping algorithm for maximizing the probability of catching the propagated evidences from functional design errors. Then, to effectively localize speedpathrelated electrical errors, we propose an innovative trace signal selection solution as well as a trace qualification technique. On the other hand, we introduce several low-cost interconnection fabrics to effectively transfer trace data in post-silicon validation. We first propose to reuse the existing test channel for real-time trace data transfer, so that the routing cost of debug hardware is dramatically reduced. The method is further improved to avoid data corruption in multi-core debug. We then develop a novel interconnection fabric design and optimization technique, by combining multiplexor network and non-blocking network, to achieve high debug flexibility with minimized hardware cost. Moreover, we introduce a hybrid trace interconnection fabric that is able to tolerate unknown values in “golden vectors“, at the cost of little extra DfD overhead. With the fabric, we develop a systematic signal tracing procedure to automatically localize erroneous signals with just a few debug runs. Our empirical evaluation shows that the solutions presented in this thesis can greatly improve the validation quality of VLSI circuits, and ultimately enable the design and fabrication of reliable electronic devices. / Liu, Xiao. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 143-152). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract --- p.i / Acknowledgement --- p.iv / Preface --- p.vii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Trends and Validation Challenges --- p.1 / Chapter 1.2 --- Key Contributions and Thesis Outline --- p.4 / Chapter 2 --- State of the Art on Post-Silicon Validation --- p.8 / Chapter 2.1 --- Trace Signal Selection --- p.12 / Chapter 2.2 --- Interconnection Fabric Design for Trace Data Transfer --- p.14 / Chapter 2.3 --- Trace Data Compression --- p.15 / Chapter 2.4 --- Trace-Based Debug Control --- p.16 / Chapter 3 --- Signal Selection for Visibility Enhancement --- p.18 / Chapter 3.1 --- Preliminaries and Summary of Contributions --- p.19 / Chapter 3.2 --- Restorability Formulation --- p.23 / Chapter 3.2.1 --- Terminologies --- p.23 / Chapter 3.2.2 --- Gate-Level Restorabilities --- p.24 / Chapter 3.3 --- Trace Signal Selection --- p.28 / Chapter 3.3.1 --- Circuit Level Visibility Calculation --- p.28 / Chapter 3.3.2 --- Trace Signal Selection Methodology --- p.30 / Chapter 3.3.3 --- Trace Signal Selection Enhancements --- p.31 / Chapter 3.4 --- Experimental Results --- p.34 / Chapter 3.4.1 --- Experiment Setup --- p.34 / Chapter 3.4.2 --- Experimental Results --- p.35 / Chapter 3.5 --- Conclusion --- p.40 / Chapter 4 --- Multiplexed Tracing for Design Error --- p.47 / Chapter 4.1 --- Preliminaries and Summary of Contributions --- p.49 / Chapter 4.2 --- Design Error Visibility Metric --- p.53 / Chapter 4.3 --- Proposed Methodology --- p.56 / Chapter 4.3.1 --- Supporting DfD Hardware for Multiplexed Signal Tracing --- p.58 / Chapter 4.3.2 --- Signal Grouping Algorithm --- p.58 / Chapter 4.4 --- Experimental Results --- p.62 / Chapter 4.4.1 --- Experiment Setup --- p.62 / Chapter 4.4.2 --- Experimental Results --- p.63 / Chapter 4.5 --- Conclusion --- p.66 / Chapter 5 --- Tracing for Electrical Error --- p.68 / Chapter 5.1 --- Preliminaries and Summary of Contributions --- p.69 / Chapter 5.2 --- Observing Speedpath-Related Electrical Errors --- p.71 / Chapter 5.2.1 --- Speedpath-Related Electrical Error Model --- p.71 / Chapter 5.2.2 --- Speedpath-Related Electrical Error Detection Quality --- p.73 / Chapter 5.3 --- Trace Signal Selection --- p.75 / Chapter 5.3.1 --- Relation Cube Extraction --- p.76 / Chapter 5.3.2 --- Signal Selection for Non-Zero-Probability Error Detection --- p.77 / Chapter 5.3.3 --- Trace Signal Selection for Error Detection Quality Enhancement --- p.78 / Chapter 5.4 --- Trace Data Qualification --- p.80 / Chapter 5.5 --- Experimental Results --- p.83 / Chapter 5.6 --- Conclusion --- p.87 / Chapter 6 --- Reusing Test Access Mechanisms --- p.88 / Chapter 6.1 --- Preliminaries and Summary of Contributions --- p.89 / Chapter 6.1.1 --- SoC Test Architectures --- p.89 / Chapter 6.1.2 --- SoC Post-Silicon Validation Architectures --- p.90 / Chapter 6.1.3 --- Summary of Contributions --- p.92 / Chapter 6.2 --- Overview of the Proposed Debug Data Transfer Framework --- p.93 / Chapter 6.3 --- Proposed DfD Structures --- p.94 / Chapter 6.3.1 --- Modified Wrapper Design --- p.95 / Chapter 6.3.2 --- Trace Buffer Interface Design --- p.97 / Chapter 6.4 --- Sharing TAM for Multi-Core Debug Data Transfer --- p.98 / Chapter 6.4.1 --- Core Masking for TestRail Architecture --- p.98 / Chapter 6.4.2 --- Channel Split --- p.99 / Chapter 6.5 --- Experimental Results --- p.101 / Chapter 6.6 --- Conclusion --- p.104 / Chapter 7 --- Interconnection Fabric for Flexible Tracing --- p.105 / Chapter 7.1 --- Preliminaries and Summary of Contributions --- p.106 / Chapter 7.2 --- Proposed Interconnection Fabric Design --- p.111 / Chapter 7.2.1 --- Multiplexer Network for Mutually-Exclusive Signals --- p.111 / Chapter 7.2.2 --- Non-Blocking Concentration Network for Concurrently-Accessible Signals --- p.114 / Chapter 7.3 --- Experimental Results --- p.117 / Chapter 7.4 --- Conclusion --- p.121 / Chapter 8 --- Interconnection Fabric for Systematic Tracing --- p.123 / Chapter 8.1 --- Preliminaries and Summary of Contributions --- p.124 / Chapter 8.2 --- Proposed Trace Interconnection Fabric --- p.128 / Chapter 8.3 --- Proposed Error Evidence Localization Methodology --- p.130 / Chapter 8.4 --- Experimental Results --- p.133 / Chapter 8.4.1 --- Experimental Setup --- p.133 / Chapter 8.4.2 --- Results and Discussion --- p.134 / Chapter 8.5 --- Conclusion --- p.139 / Chapter 9 --- Conclusion --- p.140 / Bibliography --- p.152

Based on constitutive equations of piezoelectricity and two-port modeling method, the models of piezoelectric materials are investigated. The equivalent circuit models of the piezoelectric element in the energy harvesting system are explored. It is found that there exists an optimal external impedance that gives the maximum output power. Experiments are conducted to verify the optimal impedance theory. / The energy storage devices in the piezoelectric energy harvesting system are analyzed. The charge/discharge efficiencies of the energy storage devices are mainly considered. Based on the analysis of the electric characteristics of the energy storage devices, we find the leakage resistances of the energy storage devices are the dominant factor that influences the charge/discharge efficiency in the piezoelectric energy harvesting system. A quick test method is proposed to experimentally study the charge/discharge efficiencies of the energy storage devices. The experimental results verify our findings. Adaptability, lifetime, and protection circuit of the energy storage devices are also discussed. It can be concluded that the supercapacitors are suitable and more attractive than the rechargeable batteries to store the energy in the piezoelectric energy harvesting system. / Two schemes of piezoelectric energy harvesting circuits are analyzed: one-stage and two-stage energy harvesting schemes. The efficiency of the two-stage harvesting scheme is found to be related to several factors including the energy storage device voltage. Analysis and experiments using one-stage energy harvesting circuit to harvest a varying excitation source are explored. The results show that one-stage energy harvesting scheme can achieve higher efficiency than the two-stage scheme towards a range of energy storage voltages. / Using piezoelectric elements to harvest energy from ambient vibration has been of great interest recently. Because the power harvested from the piezoelectric elements is relatively low, energy storage devices are needed to accumulate the energy for intermittent use and energy harvesting circuits are applied to transfer the electrical energy from the sources to the storage devices. Therefore, a piezoelectric energy harvesting system can be basically divided into three parts: the energy source, the energy harvesting circuit, and the energy storage device. These three parts are explored in this thesis. / Guan Mingjie. / "September 2006." / Adviser: Wei-Hsin Liao. / Source: Dissertation Abstracts International, Volume: 68-03, Section: B, page: 1822. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 123-128). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Ip, Wei Chi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 92-94). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.ii / Acknowledgement --- p.iii / Table of Content --- p.iv / Lists of Figures --- p.vii / Lists of Tables --- p.xii / Chapter Chapter 1: --- Introduction --- p.1 / Chapter 1.1 --- Research Motivation and Obj ective --- p.1 / Chapter 1.2 --- Original Contribution --- p.2 / Chapter 1.3 --- Overview of the Thesis Organization --- p.3 / Chapter 1.4 --- "Research Approach, Assumptions and Limitations" --- p.4 / Chapter Chapter 2: --- Power Divider Design Fundamentals --- p.5 / Chapter 2.1 --- Power Divider Basics --- p.5 / Chapter 2.2 --- Wilkinson Power Divider --- p.6 / Chapter 2.3 --- Power Divider with Unequal Power Division --- p.8 / Chapter 2.4 --- Multi-way Power Divider --- p.9 / Chapter 2.4.1 --- Wilkinson N-way Hybrid --- p.10 / Chapter 2.4.2 --- Radial Hybrid --- p.11 / Chapter 2.4.3 --- Fork Hybrid --- p.12 / Chapter 2.4.4 --- Multi-layer Approach --- p.IS / Chapter 2.4.5 --- Power Recombination Concept --- p.15 / Chapter 2.4.6 --- Multi-coupled-line Approach --- p.18 / Chapter Chapter 3: --- Conventional Power Divider Designs with Harmonic Suppression --- p.20 / Chapter 3.1 --- Resonating-stubs Topology --- p.20 / Chapter 3.2 --- Asymmetric Defected Ground Structure (DGS) --- p.26 / Chapter 3.3 --- Anti-Coupled Line Structure --- p.30 / Chapter 3.4 --- Microstrip Electromagnetic Bandgap (EBG) Based Topology --- p.32 / Chapter 3.5 --- Embedded Resonators Topology --- p.37 / Chapter 3.6 --- Extended Line Approach --- p.39 / Chapter Chapter 4: --- New 2-way Power Divider Design with Spurious Suppression and Impedance Transformation --- p.41 / Chapter 4.1 --- Proposed Topology --- p.41 / Chapter 4.2 --- Design and Analysis --- p.42 / Chapter 4.3 --- Simulation Study --- p.45 / Chapter 4.4 --- Experimental Verification --- p.50 / Chapter 4.5 --- Summary --- p.57 / Chapter Chapter 5: --- New 2-way Power Divider Design with Extended Spurious Suppression --- p.58 / Chapter 5.1 --- Proposed Topology --- p.58 / Chapter 5.2 --- Design and Analysis --- p.59 / Chapter 5.3 --- Simulation Study --- p.64 / Chapter 5.3 --- Experimental Verification --- p.68 / Chapter 5.4 --- Summary --- p.71 / Chapter Chapter 6: --- New 2-way Unequal Power Divider Design with Dual-harmonic Rejection --- p.72 / Chapter 6.1 --- Proposed Topology --- p.72 / Chapter 6.2 --- Design and Analysis --- p.73 / Chapter 6.3 --- Simulation Study --- p.76 / Chapter 6.4 --- Experimental Verification --- p.77 / Chapter 6.4 --- Summary --- p.80 / Chapter Chapter 7: --- New 3-way Power Divider Design with Multi-harmonic Rejection..… --- p.81 / Chapter 7.1 --- Proposed Topology --- p.81 / Chapter 7.2 --- Design and Analysis --- p.82 / Chapter 7.3 --- Simulation Study --- p.85 / Chapter 7.4 --- Experimental Verification --- p.87 / Chapter 7.4 --- Summary --- p.90 / Chapter Chapter 8: --- Conclusion --- p.91 / References --- p.92 / Author's Publications and Awards --- p.95 / Chapter Appendix 1: --- ABCD Parameters of Some Useful Two-port Circuits --- p.96 / Chapter Appendix 2: --- More Designs of Proposed Configuration in Chapter 5 --- p.97 / Chapter A2.1 --- Miniaturized version of Example 1 --- p.97 / Chapter A2.2 --- Design with improved stop-band response --- p.101 / Chapter A2.3 --- Design of prototype with 2 GHz operating frequency --- p.104 / Chapter Appendix 3: --- Brief Summary of Power Dividers with Harmonic Suppression --- p.108

To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer technology nodes. / This work presents a joint optimization scheme to consider variation, total fill, line deviation, outlier, overlap and running time simultaneously. More specifically, we first partition the rectilinear fillable regions into rectangles for later processing. Inspired by the work–PTR (Polygon-To-Rectangle) in [3], we implement I-PTR (Improved PTR) and another new decomposition algorithm called L-PTR (Lowest overlapping edge PTR) to divide the fillable regions into rectangles according to the window boundaries on one hand and to get more large resulting rectangles on the other hand. After decomposition, we insert dummy fills into the fillable rectangular regions optimizing the fill metrics simultaneously. We propose three approaches–Fast Median approach, LP approach and Iterative approach. Among the three fill insertion algorithms, Fast Median is proven to be the best. Therefore we compare Fast Median with the top three contestants in the ICCAD Contest 2014 on the industrial benchmarks released by the contest organizer. Experiments show that Fast Median is 25× faster than the fastest one among the top three teams, and its quality score (0.70) outperforms the top three teams of which the scores are 0.63, 0.61 and 0.61 respectively. / 為了降低芯片的密度差異，冗餘的金屬填充物通常會被用來提高布線板的密度均勻性。過去的研究工作要麼一味以最大化均勻性为目标，要麼在滿足一定的密度差異的基礎上以加入佈線板的金屬填充物的總量最少为目标。然而，由於更加嚴格的工業製造挑戰，很多新的目標越來越舉足輕重，比如列密度差和異常值。 / 本文提出了同時考慮總差異、填充物總量、列密度差、異常值、重疊和運行時間的優化方法。具體來說，首先我們將表示可填充區域的直角多邊形分解成矩形，方便後續的處理。受到相關工作——PTR[3]的啟發，我們實現了I-PTR和另外一種新的分解算法L-PTR來分解可填充區域，一方面，我們根據窗口邊界來分解，另一方面我們盡量分解得到更多大面積矩形。分解之後，我們將金屬填充物加入到可填充區域，同時優化各個目標函數。我們提出了三種優化方法——快速中值法，LP法和迭代法。在這三種方法當中，快速中值法被證明是最好的。所以我们将快速中值法與ICCAD 2014年競賽的前三名算法分別運用在比賽發佈的測試集上，進行對比。實驗數據表明，我們的快速中值法比前三名最快的還要快25倍。並且，我們的總得分（0.70）要優於前三名的得分（分别是0.63、0.61和0.61）。 / Liu, Chuangwen. / Thesis M.Phil. Chinese University of Hong Kong 2015. / Includes bibliographical references (leaves 59-62). / Abstracts also in Chinese. / Title from PDF title page (viewed on 12, October, 2016). / Detailed summary in vernacular field only. / Detailed summary in vernacular field only.