by Kit-man Chan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves 82-86). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview of Integrated Service Digital Networks --- p.1 / Chapter 1.2 --- Multirate Loss Networks --- p.5 / Chapter 1.3 --- Previous Work --- p.7 / Chapter 1.4 --- Organization --- p.11 / Chapter 1.5 --- Publications --- p.12 / Chapter 2 --- Call Admission in Multirate Loss Networks --- p.13 / Chapter 2.1 --- Introduction --- p.13 / Chapter 2.2 --- Two Adaptive Routing Rules --- p.15 / Chapter 2.3 --- Call Admission Policies --- p.17 / Chapter 2.4 --- Analysis of Call Admission Policies --- p.25 / Chapter 2.4.1 --- "The CS, LO, GB and the EB Policies" --- p.25 / Chapter 2.4.2 --- The DP Policy --- p.29 / Chapter 2.5 --- Performance Comparisons --- p.32 / Chapter 2.6 --- Concluding Remarks --- p.35 / Chapter 3 --- Least Congestion Routing in Multirate Loss Networks --- p.41 / Chapter 3.1 --- Introduction --- p.41 / Chapter 3.2 --- The M2 and MTB Routings --- p.42 / Chapter 3.2.1 --- M2 Routing --- p.43 / Chapter 3.2.2 --- MTB Routing --- p.43 / Chapter 3.3 --- Bandwidth Sharing Policies and State Aggregation --- p.45 / Chapter 3.4 --- Analysis of M2 Routing --- p.47 / Chapter 3.5 --- Analysis of MTB Routing --- p.50 / Chapter 3.6 --- Numerical Results and Discussions --- p.53 / Chapter 3.7 --- Concluding Remarks --- p.56 / Chapter 4 --- The Least Congestion Routing in WDM Lightwave Networks --- p.60 / Chapter 4.1 --- Introduction --- p.60 / Chapter 4.2 --- Architecture and Some Design Issues --- p.62 / Chapter 4.3 --- The Routing Rule --- p.66 / Chapter 4.4 --- Analysis of the LC Routing Rule --- p.67 / Chapter 4.4.1 --- Fixed Point Model --- p.67 / Chapter 4.4.2 --- Without Direct-link Priority --- p.68 / Chapter 4.4.3 --- With Direct-link Priority --- p.72 / Chapter 4.5 --- Performance Comparisons --- p.73 / Chapter 4.6 --- Concluding Remarks --- p.75 / Chapter 5 --- Conclusions and Future Work --- p.79 / Chapter 5.1 --- Future Work --- p.80

by Shum Kam Hong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1992. / Includes bibliographical references (leaves 125-131). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Outline of the thesis --- p.6 / Chapter 1.3 --- Current Art in Packet Switching --- p.9 / Chapter 2 --- Management of Control Information --- p.17 / Chapter 2.1 --- Inter-node Exchange of Link Congestion Status --- p.21 / Chapter 2.2 --- Consistency of Control Information --- p.24 / Chapter 2.3 --- Alternate Format of Control Information --- p.26 / Chapter 3 --- Traffic Flow Control --- p.29 / Chapter 3.1 --- Control of Traffic Influx into the Network --- p.29 / Chapter 3.2 --- Control of Traffic Loading from the Node --- p.30 / Chapter 3.3 --- Flow Control for Connection Oriented Traffic --- p.32 / Chapter 3.4 --- Judgement of Link Status --- p.38 / Chapter 3.5 --- Starvation-free and Deadlock-free --- p.42 / Chapter 4 --- Call Set-up Algorithm Traffic Modelling --- p.47 / Chapter 4.1 --- Basic Algorithm --- p.47 / Chapter 4.2 --- Minimization of Bandwidth Overhead --- p.48 / Chapter 4.3 --- Two-way Transmission --- p.51 / Chapter 4.4 --- Traffic Modelling --- p.52 / Chapter 4.4.1 --- Aggregate Traffic Models --- p.53 / Chapter 4.4.2 --- Traffic Burstiness --- p.57 / Chapter 5 --- Parameters Tuning and Analysis --- p.76 / Chapter 5.1 --- Scheme I : Scout Pumping --- p.76 / Chapter 5.2 --- Scheme II : Speed-up Scout Pumping --- p.85 / Chapter 5.3 --- Blocking Probability --- p.90 / Chapter 5.4 --- Scout Stream Collision --- p.92 / Chapter 6 --- Simulation Modelling & Performance Evaluation --- p.96 / Chapter 6.1 --- The Network Simulator --- p.96 / Chapter 6.1.1 --- Simulation Event Scheduling --- p.97 / Chapter 6.1.2 --- Input Traffic Regulation --- p.100 / Chapter 6.1.3 --- Actual Offered Load --- p.101 / Chapter 6.1.4 --- Static and Dynamic Parameters --- p.103 / Chapter 6.2 --- Simulation Results --- p.107 / Chapter 7 --- Conclusions --- p.123 / Chapter A --- List of Symbols --- p.132

Wong, Po-Choi. / Summary in Chinese. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1989. / Bibliography: leaves 156-164.

by Yeung Ming Sang. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves 191-[201]). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.1.1 --- Broadband Integrated Services Network --- p.1 / Chapter 1.1.2 --- ATM Switching Technology --- p.3 / Chapter 1.2 --- Broadband ATM Switching ´ؤ A Review --- p.4 / Chapter 1.2.1 --- Shared Memory Switches --- p.5 / Chapter 1.2.2 --- Shared Medium Switches --- p.5 / Chapter 1.2.3 --- Space-division Type Switches --- p.6 / Chapter 1.3 --- Motivation and Contributions --- p.13 / Chapter 1.4 --- Overview of the Thesis --- p.13 / Chapter 2 --- Pipeline Banyan Switch Architecture --- p.15 / Chapter 2.1 --- Switch Architecture --- p.15 / Chapter 2.2 --- Switch Operation --- p.17 / Chapter 2.3 --- Switch Design --- p.19 / Chapter 2.4 --- "Priority, Broadcasting and Multicasting Mechanisms" --- p.21 / Chapter 2.5 --- Switch Speed Reduction at the Control Plane --- p.23 / Chapter 3 --- Performance Evaluation of Pipeline Banyan --- p.27 / Chapter 3.1 --- Performance under Uniform and Independent Traffic Pattern --- p.27 / Chapter 3.1.1 --- Analysis of Packet Loss Performance --- p.27 / Chapter 3.1.2 --- Throughput Performance --- p.32 / Chapter 3.1.3 --- Delay Performance --- p.36 / Chapter 3.1.4 --- Comparison of Loss Performance of Banyan-type Networks --- p.37 / Chapter 3.1.5 --- Output Queueing Capability --- p.41 / Chapter 3.2 --- Performance of the Switch under Special Traffic Pattern --- p.45 / Chapter 3.2.1 --- Performance under Bursty Traffic --- p.45 / Chapter 3.2.2 --- Performance under Hot Spot Traffic --- p.48 / Chapter 3.2.3 --- Performance under Point-to-Point Traffic --- p.51 / Chapter 3.2.4 --- Performance under Permutation Traffic --- p.52 / Chapter 3.3 --- Switch Complexity Discussion --- p.54 / Chapter 4 --- Multi-Channel Pipeline Banyan (MCPB) --- p.57 / Chapter 4.1 --- Background --- p.57 / Chapter 4.2 --- Switch Architecture --- p.59 / Chapter 4.3 --- Performance Evaluation --- p.64 / Chapter 4.3.1 --- Packet loss probability --- p.64 / Chapter 4.3.2 --- Throughput performance --- p.69 / Chapter 4.3.3 --- Delay performance --- p.69 / Chapter 4.4 --- Application of MCPB --- p.71 / Chapter 4.4.1 --- ATM Cross-connect --- p.71 / Chapter 4.4.2 --- Switch Interconnection Fabric --- p.71 / Chapter 5 --- VLSI Implementation --- p.75 / Chapter 5.1 --- Outline of a typical ATM switching system --- p.75 / Chapter 5.1.1 --- Line Interface Module --- p.75 / Chapter 5.1.2 --- System Manager Module --- p.77 / Chapter 5.1.3 --- Switch Module --- p.78 / Chapter 5.2 --- "VLSI Design Technology, Procedures and Tools" --- p.78 / Chapter 5.2.1 --- Design Technology --- p.78 / Chapter 5.2.2 --- Procedures and Tools --- p.79 / Chapter 5.3 --- Logic Design of ATM Switch Module --- p.80 / Chapter 5.3.1 --- Switching Element in Control Plane --- p.80 / Chapter 5.3.2 --- Switching Element in Data Plane --- p.86 / Chapter 5.3.3 --- Clock Generator for Synchronization --- p.93 / Chapter 5.3.4 --- Schematic of Control Plane --- p.98 / Chapter 5.3.5 --- Schematic of Data Plane --- p.98 / Chapter 5.3.6 --- Timing Diagrams --- p.98 / Chapter 5.4 --- Chip Summary --- p.107 / Chapter 5.5 --- Experiences --- p.109 / Chapter 5.5.1 --- Core Size Limitation --- p.109 / Chapter 5.5.2 --- Pin Count Limitation --- p.110 / Chapter 5.5.3 --- Speed Limitation --- p.111 / Chapter 5.5.4 --- Other Design Considerations --- p.111 / Chapter 5.6 --- Discussions --- p.112 / Chapter 6 --- Dynamic Priority Schemes for Fast Packet Switches --- p.114 / Chapter 6.1 --- Motivation --- p.114 / Chapter 6.2 --- Switch Architecture --- p.118 / Chapter 6.3 --- QCPD: Queueing Controlled Priority Discipline --- p.121 / Chapter 6.3.1 --- Algorithm QCPD --- p.121 / Chapter 6.4 --- BCPD: Blocking Controlled Priority Discipline --- p.122 / Chapter 6.4.1 --- Algorithm BCPD_FT --- p.122 / Chapter 6.4.2 --- Delay Guarantee by Algorithm BCPD_FT --- p.123 / Chapter 6.4.3 --- Algorithm BCPD_DT --- p.126 / Chapter 6.4.4 --- Delay Guarantee by Algorithm BCPD_DT --- p.128 / Chapter 6.5 --- HCPD: Hybrid Controlled Priority Discipline --- p.134 / Chapter 6.5.1 --- Algorithms HCPD_FT and HCPD_DT --- p.135 / Chapter 6.6 --- Performance Studies --- p.136 / Chapter 6.6.1 --- Performance Comparison of the Priority Schemes --- p.136 / Chapter 6.6.2 --- Cell Loss Performance of HCPD_DT --- p.140 / Chapter 6.6.3 --- Input Queue Distribution of HCPD_DT --- p.142 / Chapter 6.6.4 --- Delay Bound of HCPD_DT --- p.144 / Chapter 6.6.5 --- Performance of HCPD_DT under Priority Traffic --- p.148 / Chapter 6.7 --- The use of HCPD_DT in Pipeline Banyan --- p.152 / Chapter 6.8 --- Conclusion --- p.153 / Chapter 7 --- Summary and Future Work --- p.155 / Chapter 7.1 --- Summary --- p.155 / Chapter 7.2 --- Future Work --- p.156 / Chapter A --- Verilog HDL descriptions of 16x16 Pipeline Banyan --- p.158 / Chapter B --- User's Guide of 16x16 Pipeline Banyan Chip Set --- p.182 / Chapter B.l --- Specification --- p.182 / Chapter B.2 --- Control Plane Chip and Data Plane Chip Pinout --- p.183 / Chapter B.2.1 --- Control Plane Chip Pinout --- p.183 / Chapter B.2.2 --- Data Plane Chip Pinout --- p.183 / Chapter B.3 --- Signal Descriptions --- p.186 / Chapter B.3.1 --- Signal Descriptions of Control Plane Chip --- p.186 / Chapter B.3.2 --- Signal Descriptions of Data Plane Chip --- p.187 / Chapter B.4 --- Connection Examples --- p.188 / Bibliography --- p.191

Lau Tsz-ming. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 57-[61]). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Integrated Services Architecture --- p.2 / Chapter 1.2 --- Cross-path Switch --- p.4 / Chapter 1.2.1 --- Path Switching --- p.5 / Chapter 1.3 --- Organization of Thesis --- p.9 / Chapter 2 --- Module Architecture --- p.10 / Chapter 2.1 --- Introduction --- p.10 / Chapter 2.2 --- Notable Features --- p.11 / Chapter 3 --- Connection Admission Control and Resource Allocation --- p.14 / Chapter 3.1 --- Introduction --- p.14 / Chapter 3.2 --- Connection Admission Control --- p.15 / Chapter 3.2.1 --- Guaranteed Service --- p.15 / Chapter 3.2.2 --- Controlled-Load Service --- p.18 / Chapter 3.3 --- Resource Allocation --- p.27 / Chapter 4 --- Resource Management --- p.31 / Chapter 4.1 --- Introduction --- p.31 / Chapter 4.2 --- Scheduling Algorithm --- p.32 / Chapter 4.2.1 --- Input and Output Module --- p.32 / Chapter 4.2.2 --- Central Module --- p.34 / Chapter 4.3 --- Buffer Management --- p.39 / Chapter 4.3.1 --- Buffer Partitioning --- p.40 / Chapter 4.3.2 --- Dicard Policy --- p.40 / Chapter 5 --- Design Issue of Cross-path Switch --- p.43 / Chapter 5.1 --- Introduction --- p.43 / Chapter 5.2 --- Stability Condition --- p.44 / Chapter 5.3 --- Supplementary Admission Control Scheme --- p.46 / Chapter 5.4 --- Simulation --- p.50 / Chapter 6 --- Conclusion --- p.55 / Bibliography --- p.57

Recently, the Birkhoff-von Neumann (BvN) switch has become a typical model for providing QoS in input-queued switch. The major idea is to consider a set of predetermined permutation matrices as independent flows, and the scheduling problem in the input-queued switch can be simply handled by single-server scheduling algorithms, such as weighted fair queueing (WFQ). However, a number of problems are observed. Firstly, although WFQ is a fair algorithm, it has a poor delay performance that depends on the port counts. Secondly, the BvN switch does not perform well under certain traffic requirement, thus unable to provide tight performance guarantees. In this thesis, a set of admission control strategies and scheduling algorithms are therefore developed to improve the QoS performance. / The input-queued switch architecture is widely used in Internet routers, due to its ability to run at very high speeds. A central problem in designing an input-queued switch is choosing the scheduling algorithm, i.e. deciding which packets to transfer from input ports to output ports in a given timeslot. Recent research in packet switch scheduling algorithms has moved beyond throughput maximization to quality of service (QoS) control. / Choy Man Ting. / "September 2006." / Adviser: Tony T. Lee. / Source: Dissertation Abstracts International, Volume: 68-03, Section: B, page: 1815. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 89-94). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

by Philip Pak-tung To. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (p. 126). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web.

by Timothy Kai-Cheung Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references. / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 2. --- ASYNCHRONOUS TRANSFER MODE SWITCHING --- p.4 / Chapter 2.1 --- Transfer Modes --- p.4 / Chapter 2.1.1 --- Circuit Switching --- p.4 / Chapter 2.1.2 --- ATM Switching --- p.6 / Chapter 2.1.3 --- Packet Switching --- p.8 / Chapter 2.2 --- Different Types of ATM Switching System --- p.8 / Chapter 2.2.1 --- Central Control Type --- p.9 / Chapter 2.2.2 --- Self-Routing Type --- p.9 / Chapter 2.3 --- Self-Routing Non-Buffering ATM Switching Node --- p.10 / Chapter 3. --- FUNCTIONAL DESCRIPTION OF MODULE ´بA´ة --- p.16 / Chapter 3.1 --- ATM Cell Format --- p.17 / Chapter 3.2 --- Concentrator --- p.17 / Chapter 3.3 --- Routing Cell --- p.19 / Chapter 4. --- PHYSICAL STRUCTURE OF MODULE ´بA´ة --- p.23 / Chapter 4.1 --- Clocking Scheme --- p.23 / Chapter 4.2 --- Concentrator --- p.25 / Chapter 4.2.1 --- 2-by-2 Sorter --- p.25 / Chapter 4.2.2 --- Input Framer --- p.30 / Chapter 4.2.3 --- Data Buffer --- p.38 / Chapter 4.3 --- Routing Cell --- p.38 / Chapter 4.3.1 --- Type I Router --- p.39 / Chapter 4.3.2 --- Type II Router --- p.42 / Chapter 4.4 --- Block By-Passed Function --- p.43 / Chapter 5. --- SIMULATION AND TEST --- p.48 / Chapter 5.1 --- Computer Simulation --- p.48 / Chapter 5.2 --- Actual Chip Testing --- p.53 / Chapter 5.3 --- Measurement Results --- p.55 / Chapter 5.3.1 --- Functionality --- p.55 / Chapter 5.3.2 --- Maximum Clock Frequency --- p.60 / Chapter 5.3.3 --- Power Dissipation --- p.61 / Chapter 6. --- CONCLUSION --- p.63 / Chapter A. --- BRIEF HISTORY OF ATM SWITCH ARCHITECTURE DEVELOPMENT --- p.65 / Chapter B. --- BIBLIOGRAPHY --- p.66 / Chapter C. --- A N-WELL CMOS PROCESS --- p.70 / Chapter D. --- CADENCE DESIGN FLOW --- p.73 / Chapter E. --- YERILOG SIMULATION PROGRAMS --- p.77 / Chapter F. --- SCHEMATIC DIAGRAMS --- p.100

The research presented in this thesis aims to demonstrate that fuzzy logic is a useful tool for developing mechanisms for controlling traffc flow in ATM based multimedia networks to maintain quality of service (QoS) requirements and maximize resource utilization. The study first proposes a hierarchical, multilevel control structure for ATM networks to exploit the reported strengths of fuzzy logic at various control levels. Then, an extensive development and evaluation is presented for a subset of the proposed control architecture at the congestion control level. An ATM based multimedia network must have quite sophisticated traffc control capabilities to effectively handle the requirements of a dynamically varying mixture of voice, video and data services while meeting the required levels of performance. Feedback control techniques have an essential role for the effective and efficient management of the resources of ATM networks. However, development of conventional feedback control techniques relies on the availability of analytical system models. The characteristics of ATM networks and the complexity of service requirements cause the analytical modeling to be very difficult, if not impossible. The lack of realistic dynamic explicit models leads to substantial problems in developing control solutions for B-ISDN networks. This limits the ability of conventional techniques to directly address the control objectives for ATM networks. In the literature, several connection admission and congestion control methods for B-ISDN networks have been reported, and these have achieved mixed success. Usually they either assume heavily simplified models, or they are too complicated to implement, mainly derived using probabilistic (steady-state) models. Fuzzy logic controllers, on the other hand, have been applied successfully to the task of controlling systems for which analytical models are not easily obtainable. Fuzzy logic control is a knowledge-based control strategy that can be utilized when an explicit model of a system is not available or, the model itself, if available, is highly complex and nonlinear. In this case, the problem of control system design is based on qualitative and/or empirically acquired knowledge regarding the operation of the system. Representation of qualitative or empirically acquired knowledge in a fuzzy logic controller is achieved by linguistic expressions in the form of fuzzy relational equations. By using fuzzy relational equations, classifications related to system parameters can be derived without explicit description. The thesis presents a new predictive congestion control scheme, Fuzzy Explicit Rate Marking (FERM), which aims to avoid congestion, and by doing so minimize the cell losses, attain high server utilization, and maintain the fair use of links. The performance of the FERM scheme is extremely competitive with that of control schemes developed using traditional methods over a considerable period of time. The results of the study demonstrate that fuzzy logic control is a highly effective design tool for this type of problems, relative to the traditional methods. When controlled systems are highly nonlinear and complex, it keeps the human insight alive and accessible at the lower levels of the control hierarchy, and so higher levels can be built on this understanding. Additionally, the FERM scheme has been extended to adaptively tune (A-FERM) so that continuous automatic tuning of the parameters can be achieved, and thus be more adaptive to system changes leading to better utilization of network bandwidth. This achieves a level of robustness that is not exhibited by other congestion control schemes reported in the literature. In this work, the focus is on ATM networks rather than IP based networks. For historical reasons, and due to fundamental philosophical differences in the (earlier) approach to congestion control, the research for control of TCP/IP and ATM based networks proceeded separately. However, some convergence between them has recently become evident. In the TCP/IP literature proposals have appeared on active queue management in routers, and Explicit Congestion Notication (ECN) for IP. It is reasonably expected that, the algorithms developed in this study will be applicable to IP based multimedia networks as well.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 143-150). Available also in a digital version from Dissertation Abstracts.