The increasing clock speed and the further reduction of the feature size in integrated circuits lead to increasing demands on the interconnecting material. Thus an increasing need for a metallization with low electrical resistance and high electromigration endurance exist. Copper can be count as a material with these properties. Since 1998 Copper interconnections are commercially manufactured for integrated circuits. Electromigration is the most lifetime limiting factor in modern integrated circuits. The main the electromigration behavior influencing parameter and especially the influence of the microstructure is unknown. In this work the influence of the grain boundaries and their properties on the electromigration is examined at sputtered (PVD) and electroplated (ECD) Copper interconnects. For this investigation microstructure mappings produced by electron backscatter diffraction (EBSD) are correlated to in-situ electromigration experiments inside the SEM to research the electromigration behavior and the diffusion paths. Microstructure analysis shows big a difference between the two investigated types of interconnects. In both a strong <111> fibre texture is observed, but the PVD Copper shows a stronger texture than the electroplated one. The texture index of the PVD interconnects is 15,9 whereas the ECD lines show an index of 3,9. The frequency densities of the grain boundary misorientation, which is important for the electromigration behavior, are very different for both films. The ECD lines show a fraction of 55% Sigma 3 twin boundaries and 40% high angle grain boundaries. In contrast the PVD interconnects show a fraction of 5% Sigma 3 twin boundaries, 75% high angle grain boundaries and 20% small angle grain boundaries. This shows that a reduction of the high angle grain boundaries is not related to a strong <111> fibre texture. With in-situ experiments correlated to microstructure analysis it is shown, that voiding at high angle grain boundaries occur in the down wind of blocking grains or sites where only Sigma 3 twin boundaries are present. Hillocks were formed at high angle grain boundaries in the upwind of blocking grains or sites where only small angle grain boundaries or Sigma 3 twin boundaries are found. By a statistical evaluation of the in-situ experiments it is shown that more than 50% of the observed electromigration damages could be ascribed clearly to a grain boundary related local mass flux divergence. At strings of high angle grain boundaries voiding at the cathode side and hillock growth at the anode side is shown. The distance between these voids and hillocks is always higher than the Blech length. As the current density increases the distance between these voids and hillocks decreases according to Blech´s law, whereby it´s valid for local divergence is shown. FIB cuts show, that hillocks on PVD lines grow non-epitaxial in contrast to hillocks on ECD lines, which show epitaxial growth. These differences of hillock´s growth may suggest different underlying growth mechanisms. Reliability testing performed on PVD Copper interconnects lead to an activation energy for electromigration of 0,77eV ± 0,07eV. The confidence interval includes reported values for surface and also grain boundary diffusion. This indicates that the electromigration in these experiments is mainly influenced by surface and grain boundary diffusion. In this work the nucleation of voids and hillocks related to the previous analysed microstructure is observed inside the SEM and correlated to high angle grain boundaries and their misorientation angle. The result of this work show that electromigration damage in Copper interconnects is mostly caused by inhomogeneities of the microstructure. In this process the high angle grain boundaries are the main diffusion path. / Mit steigender Taktrate u. weiter fortschreitender Integrationsdichte in mikroelektr. Schaltungen nehmen d. Anforderungen an d. Metallisierungsmaterial weiter zu. Es besteht d. zunehmende Forderung nach Metallisierungen mit geringem elektrischen Widerstand u. hoher Elektromigra- tionsfestigkeit. Kupfer kann als Material angesehen werden, welches d. Anforderungen erfüllt. Seit 1998 wird Kupfer als Metallisierungsmaterial in höchstintegr. Schaltun- gen eingesetzt. Die Elektromigration (EM) ist der d. Zuver- lässigkeit am meisten begrenzende Faktor in mod. mikro- elektron. Schaltungen. Die Haupteinflußgrößen auf d. Elektromigrationsverhalten u. insbes. d. Einfluß d. Gefüges ist unklar. In d. Arbeit wird an nichtpassivier- ten physikalisch (PVD) u. galvanisch (ECD) abgeschied. Kupferleitbahnen d. Einfluß d. Korngrenzen u. deren Eigenschaften auf d. Elektromigrationsverhalten untersucht. Dazu werden Gefügeanalysen mittels Kikuchi-Rückstreutechnik u. in-situ Elektromigrationsexperimente im Rasterelektron- enmikroskop gekoppelt, um d. Elektromigrationsverhalten u. d. Migrationspfade zu erforschen. Gefügeuntersuchungen zeigen, daß d. untersuchten Leitbahnen sich in ihren Gefügeeigenschaften deutl. unterscheiden. Beide Schichten zeigen e. <111> Fasertextur, wobei d. PVD-Leitbahnen e. deutl. schärfere Textur mit e. Texturfaktor von 15,9 gegenüber den ECD-Leitbahnen d. e. Texturfaktor von 3,9 aufweisen. Die Häufigkeitsverteilungen d. Korngrenz- Misorientierung, sind für d. beiden Schichten unterschiedl. Die ECD-Leitbahnen zeigen e. Anteil von 55% Sigma 3-Korngrenzen und 40% Großwinkelkorngrenzen. Die PVD- Leitbahnen hingegen weisen nur e. Anteil von 5% Sigma 3-Korngrenzen, 75% Großwinkelkorngrenzen u. 20% Kleinwin- kelkorngrenzen auf. Dadurch wird gezeigt, daß e. scharfe <111> Textur keine Reduzierung d. Großwinkelkorngrenzen zur Folge haben muß. Anhand von in-situ Experimenten gekoppelt mit Gefügeanalysen wird gezeigt, daß Porenbildung an Groß- winkelkorngrenzen hinter blockierenden Körnern oder hinter Bereichen auftritt, in d. nur Sigma 3-Korngrenzen o. Kleinwinkelkorngrenzen vorliegen. Hügelbildung tritt an Großwinkelkorngrenzen vor blockierenden Körnern o. Berei- chen auf, in denen nur Kleinwinkelkorngrenzen o. Sigma 3-Korngrenzen vorliegen. Mit e. statist. Auswertung d. in-situ Experimente wird gezeigt, daß mehr als d. Hälfte aller Elektromigrationsschädigungen bei beiden Herstellungsmethoden eindeutig auf e. korngrenzbedingte lokale Divergenz im Massenfluß zurückzuführen sind. An Ketten von Großwinkelkorngrenzen wird verdeutl., daß kathodenseitig Porenbildung und anodenseitig Hügelbildung auftritt. Der Abstand zw. Pore u. Hügel liegt hier immer oberh. d. Blechlänge. Mit zunehmender Stromdichte nimmt d. Pore-Hügel-Abstand entspr. d. Blechtheorie ab, wodurch gezeigt wird, daß d. Blechtheorie auch bei lokalen Flußdivergenzen gilt. FIB-Querschnittsanalysen zeigen, daß Hügel auf PVD-Leitbahnen nicht epitaktisch mit d. darunterliegenden Schicht verwachsen sind im Gegensatz zu Hügeln auf ECD-Leitbahnen, die teilw. e. epitaktische Verwachsung mit d. Leitbahn zeigen. Lebensdauermessungen an PVD-Leitbahnen ergeben e. Aktivierungsenergie von 0,77eV ± 0,07eV. Es ist davon auszugehen, daß das Elektromigrationsverhalten d. hier untersuchten unpassi- vierten Leitbahnen haupts. von Korngrenz- u. von Oberfläch- endiffusion beeinflußt wird. In d. Arbeit wurde zum ersten Mal an Kupferleitbahnen d. Entstehung von eit- bahnschädigungen im Zusammenhang mit dem vorher aufgenomme- nen Gefüge im Rasterelektronenmikroskop direkt beobachtet u. mit d. Korngrenzen u. d. Korngrenzwinkeln in Zusammenhang gebracht. Die Ergebnisse d. Arbeit zeigen, daß Schädigungen durch Elektromigration in Kupferleitbahnen vorw. durch Gefügeinhomogenitäten entstehen. Bei d. Prozeß sind Großwinkelkorngrenzen d. bevorzugte Diffusionspfad.

The increasing clock speed and the further reduction of the feature size in integrated circuits lead to increasing demands on the interconnecting material. Thus an increasing need for a metallization with low electrical resistance and high electromigration endurance exist. Copper can be count as a material with these properties. Since 1998 Copper interconnections are commercially manufactured for integrated circuits. Electromigration is the most lifetime limiting factor in modern integrated circuits. The main the electromigration behavior influencing parameter and especially the influence of the microstructure is unknown. In this work the influence of the grain boundaries and their properties on the electromigration is examined at sputtered (PVD) and electroplated (ECD) Copper interconnects. For this investigation microstructure mappings produced by electron backscatter diffraction (EBSD) are correlated to in-situ electromigration experiments inside the SEM to research the electromigration behavior and the diffusion paths. Microstructure analysis shows big a difference between the two investigated types of interconnects. In both a strong <111> fibre texture is observed, but the PVD Copper shows a stronger texture than the electroplated one. The texture index of the PVD interconnects is 15,9 whereas the ECD lines show an index of 3,9. The frequency densities of the grain boundary misorientation, which is important for the electromigration behavior, are very different for both films. The ECD lines show a fraction of 55% Sigma 3 twin boundaries and 40% high angle grain boundaries. In contrast the PVD interconnects show a fraction of 5% Sigma 3 twin boundaries, 75% high angle grain boundaries and 20% small angle grain boundaries. This shows that a reduction of the high angle grain boundaries is not related to a strong <111> fibre texture. With in-situ experiments correlated to microstructure analysis it is shown, that voiding at high angle grain boundaries occur in the down wind of blocking grains or sites where only Sigma 3 twin boundaries are present. Hillocks were formed at high angle grain boundaries in the upwind of blocking grains or sites where only small angle grain boundaries or Sigma 3 twin boundaries are found. By a statistical evaluation of the in-situ experiments it is shown that more than 50% of the observed electromigration damages could be ascribed clearly to a grain boundary related local mass flux divergence. At strings of high angle grain boundaries voiding at the cathode side and hillock growth at the anode side is shown. The distance between these voids and hillocks is always higher than the Blech length. As the current density increases the distance between these voids and hillocks decreases according to Blech´s law, whereby it´s valid for local divergence is shown. FIB cuts show, that hillocks on PVD lines grow non-epitaxial in contrast to hillocks on ECD lines, which show epitaxial growth. These differences of hillock´s growth may suggest different underlying growth mechanisms. Reliability testing performed on PVD Copper interconnects lead to an activation energy for electromigration of 0,77eV ± 0,07eV. The confidence interval includes reported values for surface and also grain boundary diffusion. This indicates that the electromigration in these experiments is mainly influenced by surface and grain boundary diffusion. In this work the nucleation of voids and hillocks related to the previous analysed microstructure is observed inside the SEM and correlated to high angle grain boundaries and their misorientation angle. The result of this work show that electromigration damage in Copper interconnects is mostly caused by inhomogeneities of the microstructure. In this process the high angle grain boundaries are the main diffusion path. / Mit steigender Taktrate u. weiter fortschreitender Integrationsdichte in mikroelektr. Schaltungen nehmen d. Anforderungen an d. Metallisierungsmaterial weiter zu. Es besteht d. zunehmende Forderung nach Metallisierungen mit geringem elektrischen Widerstand u. hoher Elektromigra- tionsfestigkeit. Kupfer kann als Material angesehen werden, welches d. Anforderungen erfüllt. Seit 1998 wird Kupfer als Metallisierungsmaterial in höchstintegr. Schaltun- gen eingesetzt. Die Elektromigration (EM) ist der d. Zuver- lässigkeit am meisten begrenzende Faktor in mod. mikro- elektron. Schaltungen. Die Haupteinflußgrößen auf d. Elektromigrationsverhalten u. insbes. d. Einfluß d. Gefüges ist unklar. In d. Arbeit wird an nichtpassivier- ten physikalisch (PVD) u. galvanisch (ECD) abgeschied. Kupferleitbahnen d. Einfluß d. Korngrenzen u. deren Eigenschaften auf d. Elektromigrationsverhalten untersucht. Dazu werden Gefügeanalysen mittels Kikuchi-Rückstreutechnik u. in-situ Elektromigrationsexperimente im Rasterelektron- enmikroskop gekoppelt, um d. Elektromigrationsverhalten u. d. Migrationspfade zu erforschen. Gefügeuntersuchungen zeigen, daß d. untersuchten Leitbahnen sich in ihren Gefügeeigenschaften deutl. unterscheiden. Beide Schichten zeigen e. <111> Fasertextur, wobei d. PVD-Leitbahnen e. deutl. schärfere Textur mit e. Texturfaktor von 15,9 gegenüber den ECD-Leitbahnen d. e. Texturfaktor von 3,9 aufweisen. Die Häufigkeitsverteilungen d. Korngrenz- Misorientierung, sind für d. beiden Schichten unterschiedl. Die ECD-Leitbahnen zeigen e. Anteil von 55% Sigma 3-Korngrenzen und 40% Großwinkelkorngrenzen. Die PVD- Leitbahnen hingegen weisen nur e. Anteil von 5% Sigma 3-Korngrenzen, 75% Großwinkelkorngrenzen u. 20% Kleinwin- kelkorngrenzen auf. Dadurch wird gezeigt, daß e. scharfe <111> Textur keine Reduzierung d. Großwinkelkorngrenzen zur Folge haben muß. Anhand von in-situ Experimenten gekoppelt mit Gefügeanalysen wird gezeigt, daß Porenbildung an Groß- winkelkorngrenzen hinter blockierenden Körnern oder hinter Bereichen auftritt, in d. nur Sigma 3-Korngrenzen o. Kleinwinkelkorngrenzen vorliegen. Hügelbildung tritt an Großwinkelkorngrenzen vor blockierenden Körnern o. Berei- chen auf, in denen nur Kleinwinkelkorngrenzen o. Sigma 3-Korngrenzen vorliegen. Mit e. statist. Auswertung d. in-situ Experimente wird gezeigt, daß mehr als d. Hälfte aller Elektromigrationsschädigungen bei beiden Herstellungsmethoden eindeutig auf e. korngrenzbedingte lokale Divergenz im Massenfluß zurückzuführen sind. An Ketten von Großwinkelkorngrenzen wird verdeutl., daß kathodenseitig Porenbildung und anodenseitig Hügelbildung auftritt. Der Abstand zw. Pore u. Hügel liegt hier immer oberh. d. Blechlänge. Mit zunehmender Stromdichte nimmt d. Pore-Hügel-Abstand entspr. d. Blechtheorie ab, wodurch gezeigt wird, daß d. Blechtheorie auch bei lokalen Flußdivergenzen gilt. FIB-Querschnittsanalysen zeigen, daß Hügel auf PVD-Leitbahnen nicht epitaktisch mit d. darunterliegenden Schicht verwachsen sind im Gegensatz zu Hügeln auf ECD-Leitbahnen, die teilw. e. epitaktische Verwachsung mit d. Leitbahn zeigen. Lebensdauermessungen an PVD-Leitbahnen ergeben e. Aktivierungsenergie von 0,77eV ± 0,07eV. Es ist davon auszugehen, daß das Elektromigrationsverhalten d. hier untersuchten unpassi- vierten Leitbahnen haupts. von Korngrenz- u. von Oberfläch- endiffusion beeinflußt wird. In d. Arbeit wurde zum ersten Mal an Kupferleitbahnen d. Entstehung von eit- bahnschädigungen im Zusammenhang mit dem vorher aufgenomme- nen Gefüge im Rasterelektronenmikroskop direkt beobachtet u. mit d. Korngrenzen u. d. Korngrenzwinkeln in Zusammenhang gebracht. Die Ergebnisse d. Arbeit zeigen, daß Schädigungen durch Elektromigration in Kupferleitbahnen vorw. durch Gefügeinhomogenitäten entstehen. Bei d. Prozeß sind Großwinkelkorngrenzen d. bevorzugte Diffusionspfad.

The Internet of Things (IoT) is leading the world to the Internet of Everything (IoE), where things, people, intelligent machines, data and processes will be connected together. The key to enter the era of the IoE lies in enormous sensor nodes being deployed in the massively expanding wireless sensor networks (WSNs). By the year of 2025, more than 42 billion IoT devices will be connected to the Internet. While the future IoE will bring priceless advantages for the life of mankind, one challenge limiting the nowadays IoT from further development is the ongoing power demand with the dramatically growing number of the wireless sensor nodes. To address the power consumption issue, this dissertation is motivated to investigate low-power wake-up receivers (WuRXs) which will significantly enhance the sustainability of the WSNs and the environmental awareness of the IoT. Two proof-of-concept low-power WuRXs with focuses on two different application scenarios have been proposed. The first WuRX, implemented in a cost-effective 180-nm CMOS semiconductor technology, operates at 401−406-MHz band. It is a good candidate for application scenarios, where both a high sensitivity and an ultra-low power consumption are in demand. Concrete use cases are, for instance, medical implantable applications or long-range communications in rural areas. This WuRX does not rely on a further assisting semiconductor technology, such as MEMS which is widely used in state-of-the-art WuRXs operating at similar frequencies. Thus, this WuRX is a promising solution to low-power low-cost IoT. The second WuRX, implemented in a 45-nm RFSOI CMOS technology, was researched for short-range communication applications, where high-density conventional IoT devices should be installed. By investigation of the WuRX for operation at higher frequency band from 5.5 GHz to 7.5 GHz, the nowadays ever more over-traffic issues that arise at low frequency bands such as 2.4 GHz can be substantially addressed. A systematic, analytical research route has been carried out in realization of the proposed WuRXs. The thesis begins with a thorough study of state-of-the-art WuRX architectures. By examining pros and cons of these architectures, two novel architectures are proposed for the WuRXs in accordance with their specific use cases. Thereon, key WuRX parameters are systematically analyzed and optimized; the performance of relevant circuits is modeled and simulated extensively. The knowledge gained through these investigations builds up a solid theoretical basis for the ongoing WuRX designs. Thereafter, the two WuRXs have been analytically researched, developed and optimized to achieve their highest performance. Proof-of-concept circuits for both the WuRXs have been fabricated and comprehensively characterized under laboratory conditions. Finally, measurement results have verified the feasibility of the design concept and the feasibility of both the WuRXs.

In this paper, we present the design guidelines for a tunable optical isolator in an SOI-based ring resonator with two small time-modulated regions. By considering a physical model, the proper geometrical and modulation parameters are designed, based on a standard CMOS foundry process. The effect of the variation of the key parameters on the performance of the isolator is explained by two counter-acting mechanisms, namely the separation between the resonance frequencies of counter-rotating modes and energy transfer to the side harmonic. We show that there is a trade-off between these parameters to obtain maximum isolation. Consequently, by applying the quadrature phase difference one can obtain the maximum separation between the resonance frequencies and hence the minimum insertion loss, while the maximum isolation is obtained at the modulation phase difference of −0.78π , which leads to a higher insertion loss. Robustness of the design is investigated through a sensitivity analysis for the fabrication variations in the distance and width of the modulated regions. We demonstrate that there is a trade-off between isolation and insertion loss, and by varying the modulation parameters, we can achieve isolation of 18 (5) dB with 7 (1.8) dB insertion loss.

A compact device model along with simulations and an experimental analysis of a forward-biasedPNjunction-based silicon Mach-Zehndermodulator (MZM) with a phase-shifter length of 0.5 mm is presented. By placing the PN junction to a certain off-center such that72%of thewaveguide is p-doped, the refractive index swing at a given drive voltage swing is increased by 2% compared to the symmetric layout. The effects of the phase shifters’ length mismatch and asymmetric splitting on the modulation efficiency and extinction ratio of the modulator are simulated and compared with experimental results.Without any pre-emphasis or post-processing, a high-speed operation up to 15 Gb/s using a nonreturn-to-zero modulation format is demonstrated. A modulation efficiency (V πL) as low as 0.07 V × cm is verified and power consumption of 0.88 mW/Gb/s is recorded while a high extinction ratio of 33 dB is experimentally demonstrated. Compared to previously reported forward-biased silicon integrated modulators, without active tuning of the power splitting ratio between the arms, the extinction ratio is 10 dB higher. This MZM along with its compact structure is also sufficiently energy-efficient due to its low power consumption. Thus, it can be suitable for applications like analog signal processing and high-order amplitude modulation transmissions.