Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this thesis, three practical interconnect delay and slew analysis methods are presented to facilitate efficient evaluation of wire performance variability. The first method is described in detail in Chapter III. It harnesses a collection of computationally efficient procedures and closed-form formulas. By doing so, process variations are directly mapped into the variability of the output delay and slew. This method can provide the closed-form formulas of the output delay and slew at any sink node of the interconnect nets fully parameterized, in-process variations. The second method is based on adjoint sensitivity analysis and driving point model. It constructs the driving point model of the driver which drives the interconnect net by using the adjoint sensitivity analysis method. Then the driving point model can be propagated through the interconnect network by using the first method to obtain the closedform formulas of the output delay and slew. The third method is the generalized second-order adjoint sensitivity analysis. We give the mathematical derivation of this method in Chapter V. The theoretical value of this method is it can not only handle this particular variational interconnect delay and slew analysis, but it also provides an avenue for automatical linear network analysis and optimization. The proposed methods not only provide statistical performance evaluations of the interconnect network under analysis but also produce delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. Experimental results show that superior accuracy can be achieved by our proposed methods.

A new design is presented for a wideband orthogonal interconnect between two perpendicular printed wiring boards, employing novel geometries and materials to minimize stress under cyclic loading. This will ensure fatigue survivability in high vibration environments, opening the door to vertical interconnection in RF circuit design. This is, to the best of knowledge, the first complete design and prototype for an orthogonal interconnect at the board level for broadband RF circuits. An analytical approach is used to define the driving parameters in the stress distribution within a smooth curve joining two perpendicular surfaces using analytical geometries, and Finite Element Analysis is used to finalize the design and ensure all constituent materials in the interconnect are subjected to stresses below their fatigue strength at 10 million cycles at full deflection. A manufacturing process is then proposed using thermoforming to shape the Liquid Crystal Polymer base material into the desired geometry, as well as an assembly solution to mount the interconnect to an RF signal feed card. Finally, a test setup is designed allowing for high cycle fatigue testing within the order of hours, including the capability to monitor performance of the interconnect by tracking DC continuity through a simulated application using a single post design. The prototype interconnect is tested to failure and is shown to survive 18 million cycles of a typical loading application before failure of the LCP springs occurs in the mode predicted by the initial FEA model.

The median-times-to-failure (t₅₀’s) for straight dual-damascene via-terminated copper interconnect structures, tested under the same conditions, depend on whether the vias connect down to underlaying leads (metal 2, M2, or via-below structures) or connect up to overlaying leads (metal 1, M1, or via-above structures). Experimental results for a variety of line lengths, widths, and numbers of vias show higher t₅₀’s for M2 structures than for analogous M1 structures. It has been shown that despite this asymmetry in lifetimes, the electromigration drift velocity is the same for these two types of structures, suggesting that fatal void volumes are different in these two cases. A numerical simulation tool based on the Korhonen model has been developed and used to simulate the conditions for void growth and correlate fatal void sizes with lifetimes. These simulations suggest that the average fatal void size for M2 structures is more than twice the size of that of M1 structures. This result supports an earlier suggestion that preferential nucleation at the Cu/Si₃N₄ interface in both M1 and M2 structures leads to different fatal void sizes, because larger voids are required to span the line thickness in M2 structures while smaller voids at the base of vias can cause failures in M1 structures. However, it is also found that the fatal void sizes corresponding to the shortest-times-to-failure (STTF’s) are similar for M1 and M2, suggesting that the voids that lead to the shortest lifetimes occur at or in the vias in both cases, where a void need only span the via to cause failure. Correlation of lifetimes and critical void volumes provides a useful tool for distinguishing failure mechanisms. / Singapore-MIT Alliance (SMA)

Disaster support and recovery generally involve highly irregular and dangerous environments. Modular robots are a salient solution to support search and rescue efforts but are still limited to do their reliance on a rigid structure design. To enhance flexibility and resilience to damage, a soft-body interconnection mechanism for self-reconfigurable modular robotic systems has been developed. The soft-body interconnection mechanism utilizes elastomeric polymers instead of a rigid body. Hence, it is capable of deforming under extreme loads without damage. This thesis presents the work completed towards the realization of a soft-body interconnection mechanism. The functional requirements of the soft-body mechanism were broken down into two separate modules for extension and capture. An initial simulation demonstrated the inability of using a simulated model made of hypo-elastic materials as a basis for design. Hence, an iterative design process was used to develop an initial extension and capture soft-body mechanisms that conformed to the desired performance parameters. An empirical study which varied multiple structural parameters was then completed with the initial extension and capture soft-body mechanisms as a basis for the modified designs. The data from the study was correlated with measured performance data with resulted in diagrams useful for the optimal design of soft-body extension and capture mechanisms. The use of the diagrams for design was demonstrated in the design and development of a soft-body interconnection mechanism for an in-house designed small hard shell modular robot system.

The trend to integrate more and more processing cores and memory cores into a single module has increased the overall size of chips to the point where global interconnects between sub-units are becoming harder and harder to route and meet timing rules and requirements. The traditional way of routing interconnects and the use of uniform, unidirectional, point to point busses may no longer be optimal for certain designs where metal layers and chip area for interconnects are limited. The need for a more flexible routing methodology is necessary and can be achieved by using routing and calibration techniques currently being implemented at board level design. This report proposes the use of non-uniform, bidirectional, and possibly multi-point loads global interconnects within a single chip module through the use of on chip calibration techniques to compensate for less restrictive wiring rules for certain chip designs. This report will also apply a widely used digital calibration technique to simulate the implementation on a field programmable gate array. / text

Microtubules (MTs), whose basic units are a and ß tubulin proteins, are self-assembled proteinaceous filaments with nanometer scale diameters and micrometer scale lengths. Their aspect ratio, directionality, the reversibility of their assembly and their ability to be metallized by electroless plating make them good candidates to serve as templates for the fabrication of nanowires and other nanoscale devices. In addition, tubulin proteins can provide biological interactions with a naturally high specificity.Toward the goal of manufacturing MT-based metallic nanowires and networks of nanowires on a silicon wafer, I studied the influence of pH, temperature, and several biomolecules on the stability of MTs in solutions, as well as the surface effect on the dynamics of disassembly of microtubules. Secondly, I demonstrated the metallization of MTs by electroless nickel plating both in solution and on hydrophilic oxidized Si surface. After being activated by Pt, nickel coated MT surfaces during the electroless plating, with a thickness of several nanometers. Due to the different kinetics of the process, MTs metallized on the oxidized Si wafer are slightly different from MTs metallized in solutions. Finally, we explored controlled nucleation and growth of microtubules directly from a collection of g-tubulin monomers. g-tubulins bind to modified gold electrodes on a silicon wafer through an organic linker, Glutathione s-transferase, creating a g-tubulin layer for MT growth. MTs unambiguously originated from the surface-bound g-tubulin layer on the gold electrode, proving that the surface-bound g-tubulin retains its biological ability of nucleating MT growth.

In embedded computer systems there are often tasks, implemented as stand-alone devices, that are both application-specific and compute intensive. A recurring problem in this area is to design these application-specific embedded systems as close to the power and efficiency envelope as possible. Work has been done on optimizing singlecore systems and memory organisation, but current methods for achieving system design goals are proving limited as the system capabilities and system size increase in the multi- and many-core era. To address this problem, this thesis investigates machine learning approaches to managing the design space presented in the interconnect design of embedded multi-core systems. The design space presented is large due to the system scale and level of interconnectivity, and also feature inter-dependant parameters, further complicating analysis. The results presented in this thesis demonstrate that machine learning approaches, particularly wkNN and random forest, work well in handling the complexity of the design space. The benefits of this approach are in automation, saving time and effort in the system design phase as well as energy and execution time in the finished system.

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In this paper we describe an approach for generating geometrically-parameterized integrated-circuit interconnect models that are efficient enough for use in interconnect synthesis. The model generation approach presented is automatic, and is based on a multi-parameter model-reduction algorithm. The effectiveness of the technique is tested using a multi-line bus example, where both wire spacing and wire width are considered as geometric parameters. Experimental results demonstrate that the generated models accurately predict both delay and cross-talk effects over a wide range of spacing and width variation. / Singapore-MIT Alliance (SMA)