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SaskPower has two separate systems, namely the North and the South systems. The South system contains SaskPower major generation and system load. The North system load is located relatively far from its generation (200 to 300 km). The North system is considered, therefore, to be electrically weaker than the South system. Recently there has been an interest in connecting the two systems to improve the security, stability and reliability of the integrated system. Grid interconnections, however, especially between weak and strong systems, often result in the arising of low-frequency oscillations between the newly connected areas. These oscillations that are termed “inter-area oscillations” exhibit, generally poor damping and can severely restrict system operations by requiring the curtailment of electric power transfers level as an operational measure. There are two options for SaskPower North and South systems interconnection, namely HVAC and HVDC interconnections (tie-lines). This thesis reports the results of digital timedomain simulation studies carried out to investigate the dynamic performance of a proposed 260 km, 138 kV double-circuit HVAC tie-line incorporating a hybrid three-phase Thyristor- Controlled Series Capacitor (TCSC) compensation scheme that would connect the SaskPower North and South systems. The potential problems that might arise due to such an interconnection, namely power flow control and low-frequency oscillations are studied and quantified and a feasible solution is proposed. In this context, the effectiveness of the TCSC compensation scheme in damping power system oscillations in the tie-line is investigated. Time-domain simulations were conducted on the benchmark model using the ElectroMagnetic Transients Program (EMTP-RV). The results of the investigations demonstrate that the proposed HVAC link that incorporates a TCSC compensation scheme is effective in mitigating the low-frequency oscillations between the North and South systems for different system contingencies and operating conditions.

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<p>In the field of embedded computer and communication systems, the demands for the </p><p>interconnection networks are increasing rapidly. To satisfy these demands much advancement has </p><p>been made at the chip level as well as at the system level and still the research works are going </p><p>on, to make the interconnection networks more flexible to satisfy the demands of the real-time </p><p>applications. </p><p> </p><p>This thesis mainly focuses on the interconnection between the nodes in an embedded system via a </p><p>reconfigurable backplane. To satisfy the project goals, an algorithm is written for the </p><p>reconfigurable topology that changes according to the given traffic specification like throughput. </p><p>Initially the connections are established between pairs of nodes according to the given throughput </p><p>demands. By establishing all the connections, a topology is formed. Then a possible path is </p><p>chosen for traversing the data from source to destination nodes. Later the algorithm is </p><p>implemented by simulation and the results are shown in a tabular form. Through some application </p><p>examples, we both identify problems with the algorithm and propose an improvement to deal </p><p>with such problems.</p>

Banyan networks comprise a large class of networks that have been used for interconnection in large-scale multiprocessors and telephone switching systems. Regular variants of Banyan networks, such as delta and butterfly networks, have been used in multiprocessors such as the IBM RP3 and the BBN Butterfly. Analysis of the performance of Banyan networks has typically focused on these regular variants. We present a methodology for performance analysis of unbuffered Banyan multistage interconnection networks. The methodology has two novel features: it allows analysis of networks where some inputs are more likely to be active than others, and allows analysis of Banyan networks of arbitrary topology.

In the field of embedded computer and communication systems, the demands for the interconnection networks are increasing rapidly. To satisfy these demands much advancement has been made at the chip level as well as at the system level and still the research works are going on, to make the interconnection networks more flexible to satisfy the demands of the real-time applications. This thesis mainly focuses on the interconnection between the nodes in an embedded system via a reconfigurable backplane. To satisfy the project goals, an algorithm is written for the reconfigurable topology that changes according to the given traffic specification like throughput. Initially the connections are established between pairs of nodes according to the given throughput demands. By establishing all the connections, a topology is formed. Then a possible path is chosen for traversing the data from source to destination nodes. Later the algorithm is implemented by simulation and the results are shown in a tabular form. Through some application examples, we both identify problems with the algorithm and propose an improvement to deal with such problems.

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Due to the ever-shrinking feature size in CMOS process technology, it is expected that future chip multiprocessors (CMPs) will have hundreds or thousands of processing cores. To support a massively large number of cores, packet-switched on-chip interconnection networks have become a de facto communication paradigm in CMPs. However, the on-chip networks have several drawbacks, such as limited on-chip resources, increasing communication latency, and insufficient communication bandwidth. In this dissertation, several schemes are proposed to accelerate communication in on-chip interconnection networks within area and cost budgets to overcome the problems. First, an early transition scheme for fully adaptive routing algorithms is proposed to improve network throughput. Within a limited number of resources, previously proposed fully adaptive routing algorithms have low utilization in escape channels. To increase utilization of escape channels, it transfers packets earlier before the normal channels are full. Second, a pseudo-circuit scheme is proposed to reduce network latency using communication temporal locality. Reducing per-hop router delay becomes more important for communication latency reduction in larger on-chip interconnection networks. To improve communication latency, the previous arbitration information is reused to bypass switch arbitration. For further acceleration, we also propose two aggressive schemes, pseudo-circuit speculation and buffer bypassing. Third, two handshake schemes are proposed to improve network throughput for nanophotonic interconnects. Nanophotonic interconnects have been proposed to replace metal wires with optical links in on-chip interconnection networks for low latency and power consumptions as well as high bandwidth. To minimize the average token waiting time of the nanophotonic interconnects, the traditional credit-based flow control is removed. Thus, the handshake schemes increase link utilization and enhance network throughput.