Suspensions play a crucial role in vehicle comfort and stability. Different types of suspensions have been proposed to fulfill the essential characteristics of vehicle suspensions. A semi-active suspension with adjustable damper improves the performance of a suspension in different conditions and it is better than a passive suspension in terms of ride comfort and handling. Furthermore, it is not as expensive and complicated as an active suspension. Semi-active suspensions rely on adjustable damping coefficient. A new type of air suspension with independent ride height and stiffness tuning has been developed recently. By using two air chambers in the suspension system, ride height of vehicle and stiffness of suspension can be adjusted independently and simultaneously. The conventional air suspension systems use compressor to pump the air into a single flexible rubber airbag and by inflating the air, the chassis will be raised from the axle (ride height control). In this type of suspensions, the stiffness of spring is not under control. In the new air suspension system, by controlling the air pressure on both chambers, one can tune the suspension stiffness and the ride height of the vehicle at the same time for different driving conditions. The air suspension is also able to maintain the vehicle body at the same height and natural frequency for different load or number of passengers. This thesis discusses about the design analysis of an air suspension with ride height and stiffness tuning. The analytical formulation is developed for the optimum design of the new air suspension system. In this thesis, the interconnection between the pressurized chambers of the new air suspension with ride height and stiffness tuning is studied to further improve the performance. Proper interconnection of air springs can help the suspension system to distribute the load between tires more evenly on rough roads or uneven surfaces. Different configurations in air spring interconnection have different impact on the handling and tire load distribution. To study the effect of air spring interconnection configurations on tires load distribution and vehicle handling, a general mathematical model is developed. This model is used to compare various configurations in detail. Results show that interconnection could improve tire load distributions greatly. It is also shown that improving tire load distribution will deteriorate roll stiffness that in turn deteriorate vehicle handling at higher speeds. Since on rough roads, vehicle’s speed is necessarily low, interconnection will not have adverse effects on vehicle handling when activated.

SaskPower has two separate systems, namely the North and the South systems. The South system contains SaskPower major generation and system load. The North system load is located relatively far from its generation (200 to 300 km). The North system is considered, therefore, to be electrically weaker than the South system. Recently there has been an interest in connecting the two systems to improve the security, stability and reliability of the integrated system. Grid interconnections, however, especially between weak and strong systems, often result in the arising of low-frequency oscillations between the newly connected areas. These oscillations that are termed “inter-area oscillations” exhibit, generally poor damping and can severely restrict system operations by requiring the curtailment of electric power transfers level as an operational measure. There are two options for SaskPower North and South systems interconnection, namely HVAC and HVDC interconnections (tie-lines). This thesis reports the results of digital time-domain simulation studies that are carried out to investigate the dynamic performance of a proposed 260 km, ± 110 kV, 50 MW Voltage-Sourced Converter HVDC tie-line that would connect SaskPower North and South systems. The potential problems that might arise due to such an interconnection, namely power flow control and low-frequency oscillations are studied and quantified and a proposed feasible solution is presented. In this context, the effectiveness of the HVDC and a Power Oscillations Damping (POD) controller in damping power system oscillations in the tie-line is investigated. Time-domain simulations are conducted on the benchmark model using the ElectroMagnetic Transients program (EMTP-RV). The results of the investigations have demonstrated that the presented HVDC link and its POD controller are effective in mitigating the low-frequency oscillations between the North and South systems at different system contingencies and operating conditions.

This dissertation addresses the politics of interrelation between living beings and the natural world within Caribbean literature, and the underlying dangers inherent in modes of existence that deny such interrelation. Spiralism is a chaotic and pluralist literary movement emerging from Haiti in the 1960s, and this project features René Philoctète’s Spiralist novel Le Peuple des terres mêlées (1989) as its literary center, joined with two other Caribbean novels: Jacques Roumain’s Gouverneurs de la rosée (1944), and Mayra Montero’s Tú, la oscuridad (1995). In my comparative reading of these novels, I argue that their representations of environmental consciousness, social collaboration, and all-inclusive modes of interacting with the natural world provide models of co-existence in the context of the many socio-environmental injustices that threaten the continuation of many life forms on Earth, including humans. These novels evoke empathy and imagination, and add vital perspectives to the understudied field of environmentally conscious literature. Each of these three novels emotionally engages and reconnects humans as members of ecosystems – a move often lacking in the objective presentation of environmental studies. Given that the Earth is our only home, the continued ecological devastation caused by the human species increasingly deserves our full attention. I argue that the all-inclusive Spiralist imaginary and the related literatures are apt ideological tools to help address the cognitive dissonance currently preventing sufficient social change.

As the semiconductor technology scales into deeper sub-micron domain, billions of transistors can be used on a single system-on-chip (SOC) makes interconnection optimization more important roughly for two reasons. First, congestion, power, timing in routing and buffering requirements make inter- connection optimization more and more challenging. Second, gate delay get- ting shorter while the RC delay gets longer due to scaling. Study of interconnection construction and optimization algorithms in real industry flows and designs ends up with interesting findings. One used to be overlooked but very important and practical problem is how to utilize over- the-block routing resources intelligently. Routing over large IP blocks needs special attention as there is almost no way to insert buffers inside hard IP blocks, which can lead to unsolvable slew/timing violations. In current design flows we have seen, the routing resources over the IP blocks were either dealt as routing blockages leading to a significant waste, or simply treated in the same way as outside-the-block routing resources, which would violate the slew constraints and thus fail buffering. To handle that, this work proposes a novel buffering-aware over-the- block rectilinear Steiner minimum tree (BOB-RSMT) algorithm which helps reclaim the “wasted” over-the-block routing resources while meeting user-specified slew constraints. Proposed algorithm incrementally and efficiently migrates initial tree structures with buffering-awareness to meet slew constraints while minimizing wire-length. Moreover, due to the fact that timing optimization is important for the VLSI design, in this work, timing-driven over-the-block rectilinear Steiner tree (TOB-RST) is also studied to optimize critical paths. This proposed TOB-RST algorithm can be used in routing or post-routing stage to provide high-quality topologies to help close timing. Then a follow-up problem emerges: how to accomplish the whole routing with over-the-block routing resources used properly. Utilizing over-the- block routing resources could dramatically improve the routing solution, yet require special attention, since the slew, affected by different RC on different metal layers, must be constrained by buffering and is easily violated. Moreover, even of all nets are slew-legalized, the routing solution could still suffer from heavy congestion problem. A new global router, BOB-Router, is to solve the over-the-block global routing problem through minimizing overflows, wire-length and via count simultaneously without violating slew constraints. Based on my completed works, BOB-RSMT and BOB-Router tremendously improve the overall routing and buffering quality. Experimental results show that proposed over-the-block rectilinear Steiner tree construction and routing completely satisfies the slew constraints and significantly outperforms the obstacle-avoiding rectilinear Steiner tree construction and routing in terms of wire-length, via count and overflows. / text

The aim of this research is to explore the regulation of interconnection in Rwanda by investigating whether the current interconnection regime has ensured fair and reasonable interconnection rates that can enhance efficiency and effective competition. A qualitative research approach was used and the data were collected using semi-structured interviews and documentary analysis. The findings reveal that although RURA adopted a cost-based interconnection approach to ensure a fair and reasonable interconnection rate, its poor implementation resulted in an inefficient level of fixed and mobile interconnection rates. The study found an inconsistent application of the regime by incumbents, lack of sufficient regulatory capacity and lack of clear and comprehensive policy instruments. More recently, RURA is making efforts towards adopting a new regime to address the current interconnection rate issues in Rwanda. This study demonstrates that the current interconnection rate regime requires extensive rethinking about appropriate costing models and regulatory capacity, in order to enhance market efficiency and promote effective competition.

Throughout history, humankind has looked to the natural world for understanding the foundations of life and the essence of existence. Emphasizing states of sedimentary material, as physical and metaphorical reference to the cyclical complexion of life/death, growth/decay, transformation/stasis…I investigate the meaning of familial roots, reimagining humanity’s relationship to earth. The ways in which this connection can be understood are dependent on visual or symbolic representations and through experiential knowledge of sensing physicality and materiality.

Parallel computing has long been an area of research interest because exploiting parallelism in difficult problems has promised to deliver orders of magnitude speedups. Processors are now both powerful and cheap, so that systems incorporating tens, hundreds or even thousands of powerful processors need not be prohibitively expensive. The weak link in exploiting parallelism is the means of communication between the processors. Shared memory systems are fundamentally limited in the number of processors they can utilise. To achieve high levels of parallelism it is still necessary to use distributed memory and some form of interconnection network. But interconnection networks can be costly, slow, difficult to build and expand, vulnerable to faults and limited in the range of problems they can be used to solve effectively. As a result there has been extensive research into developing interconnection networks which overcome some or all of these difficulties. In this thesis it is argued that a new interconnection network, Hierarchical Cliques (HiC), and a derivative, FatHiC, possesses many desirable properties and are worthy of consideration for use in building parallel computers. A fundamental element of an interconnection network is its topology. After defining the topology of HiC, expressions are derived for the various parameters which define its underlying limits of performance and fault tolerance. A second element of an interconnection network is an addressing and routing scheme. The addressing scheme and routing algorithms of HiC are described. The flexibility of HiC is demonstrated by developing embeddings of popular, regular interconnection networks. Some embeddings into HiC suffer from high congestion, however the FatHiC network is shown to have low congestion for those embeddings. The performance of some important, regular, data parallel problems on HiC and ++ / FatHiC are determined by analysis and simulation, using the 2D-mesh as a means of comparison. But performance alone does not tell the whole story. Any parallel computer system must be cost effective. In order to analyse the cost effectiveness of HiCs an existing measure was expanded to provide a more realistic model and a more accurate means of comparison. One aim of this thesis is to demonstrate the suitability of HiC for parallel computing systems which execute irregular algorithms requiring dynamic load balancing. A new dynamic load balancing algorithm is proposed which takes advantage of the hierarchical structure of the HiC to reduce communication overheads incurred when distributing work. To demonstrate performance of an irregular problem, a novel parallel algorithm was developed to detect subgraph isomorphism from many model graphs to a single input graph. The use of the new load balancing algorithm in conjunction with the subgraph isomorphism algorithm is discussed.

There has been a move recently in academia, industry, and the consumer space towards the use of unsupervised parallel computation and distributed networks (i.e., networks of computing elements working together to achieve a global outcome with only local knowledge). To fully understand the types of problems that these systems are applied to regularly, a representative member of this group of unsupervised parallel and distributed systems is needed to allow the development of generalizable results. Although not the only potential candidate, the field of cellular automata is an excellent choice for analyzing how these systems work as it is one of the simplest members of this group in terms of design specification. The current ability of the field of cellular automata to represent the realm of unsupervised parallel and distributed systems is limited to only a subset of the possible systems, which leads to the main goal of this work of finding a method of allowing cellular automata to represent a much larger range of systems. To achieve this goal, a conceptual framework has been developed that allows the definition of interconnected systems of cellular automata that can represent most, if not all, unsupervised parallel and distributed systems. The framework introduces the concept of allowing the boundary conditions of a cellular automaton to be defined by a separately specified system, which can be any system that is capable of producing the information needed, including another cellular automaton. Using this interconnection concept, two forms of computational simplification are enabled: the deconstruction of a large system into smaller, modular pieces; and the construction of a large system built from a heterogeneous set of smaller pieces. This framework is formally defined using an interconnection graph, where edges signify the flow of information from one node to the next and the nodes are the various systems involved. A library has been designed which implements the interconnection graphs defined by the framework for a subset of the possible nodes, primarily to allow an exploration of the field of cellular automata as a potential representational member of unsupervised parallel and distributed systems. This library has been developed with a number of criteria in mind that will allow it to be instantiated on both hardware and software using an open and extendable architecture to enable interaction with external systems and future expansion to take into account novel research. This extendability is discussed in terms of combining the library with genetic algorithms to find an interconnected system that will satisfy a specific computational goal. There are also a number of novel components of the library that further enhance the capabilities of potential research, including methods for automatically building interconnection graphs from sets of cellular automata and the ability to skip over static regions of a given cellular automaton in an intelligent way to reduce computation time. With a particular set of cellular automaton parameters, the use of this feature reduced the computation time by 75%. As a demonstration of the usefulness of both the library and the framework that it implements, a hardware application has been developed which makes use of many of the novel aspects that have been introduced to produce an interactive art installation named 'Aurora'. This application has a number of design requirements that are directly achieved through the use of library components and framework definitions. These design requirements included a lack of centralized control or data storage, a need for visibly dynamic behaviour in the installation, and the desire for the visitors to the installation to be able to affect the visible movement of patterns across the surface of the piece. The success of the library in this application was heavily dependent on its instantiation on a mixture of hardware and software, as well as the ability to extend the library to suit particular needs and aspects of the specific application requirements. The main goal of this thesis research, finding a method that allows cellular automata to represent a much larger range of unsupervised parallel and distributed systems, has been partially achieved in the creation of a novel framework which defines the concept of interconnection, and the design of an interconnection graph using this concept. This allows the field of cellular automata, in combination with the framework, to be an excellent representational member of an extended set of unsupervised parallel and distributed systems when compared to the field alone. A library has been developed that satisfies a broad set of design criteria that allow it to be used in any future research built on the use of cellular automata as this representational member. A hardware application was successfully created that makes use of a number of novel aspects of both the framework and the library to demonstrate their applicability in a real world situation.

Traditionally, the microprocessor design has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip continues to increase, the design of communication architecture has become a crucial and dominating factor in defining performance models of the overall system. On-chip networks, also known as Networks-on-Chip (NoC), emerged recently as a promising architecture to coordinate chip-wide communication. Although there are numerous interconnection network studies in an inter-chip environment, an intra-chip network design poses a number of substantial challenges to this well-established interconnection network field. This research investigates designs and applications of on-chip interconnection network in next-generation microprocessors for optimizing performance, power consumption, and area cost. First, we present domain-specific NoC designs targeted to large-scale and wire-delay dominated L2 cache systems. The domain-specifically designed interconnect shows 38% performance improvement and uses only 12% of the mesh-based interconnect. Then, we present a methodology of communication characterization in parallel programs and application of characterization results to long-channel reconfiguration. Reconfigured long channels suited to communication patterns enhance the latency of the mesh network by 16% and 14% in 16-core and 64-core systems, respectively. Finally, we discuss an adaptive data compression technique that builds a network-wide frequent value pattern map and reduces the packet size. In two examined multi-core systems, cache traffic has 69% compressibility and shows high value sharing among flows. Compression-enabled NoC improves the latency by up to 63% and saves energy consumption by up to 12%.

In today's high performance computing environment I/O remains the main bottleneck in achieving the optimal performance expected of the ever improving processor and memory technologies. Interconnection networks therefore combines processing units, system I/O and high speed switch network fabric into a new paradigm of I/O based network. It decouples the system into computational and I/O interconnections each allowing "any-to-any" communications among processors and I/O devices unlike the shared model in bus architecture. The computational interconnection, a network of processing units (compute-nodes), is used for inter-processor communication in carrying out computation tasks, while the I/O interconnection manages the transfer of I/O requests between the compute-nodes and the I/O or storage media through some dedicated I/O processing units (I /O-nodes). Considering the special functions performed by the I/O nodes, their placement and reliability become important issues in improving the overall performance of the interconnection system. This thesis focuses on design and topological placement of I/O-nodes in torus based interconnection networks, with the aim of reducing I/O communication latency between compute-nodes and I/O-nodes even in the presence of faulty I/O-nodes. We propose an efficient and scalable relaxed quasi-perfect placement scheme using Lee distance error correction code such that compute-nodes are at distance-t or at most distance-t+1 from an I/O-node for a given t. This scheme provides a better and optimal alternative placement than quasi perfect placement when perfect placement cannot be found for a particular torus. Furthermore, in the occurrence of faulty I/O-nodes, the placement scheme is also used in determining other alternative I/O-nodes for rerouting I/O traffic from affected compute-nodes with minimal slowdown. In order to guarantee the quality of service required of inter-processor communication, a scheduling algorithm was developed at the router level to prioritize message forwarding according to inter-process and I/O messages with the former given higher priority. Our simulation results show that relaxed quasi-perfect outperforms quasi-perfect and the conventional I/O placement (where I/O nodes are concentrated at the base of the torus interconnection) with little degradation in inter-process communication performance. Also the fault tolerant redirection scheme provides a minimal slowdown, especially when the number of faulty I/O nodes is less than half of the initial available I/O nodes.